Microchip Technology MA330031-2 Data Sheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 332
2011-2013 Microchip Technology Inc.
bit 0
CH123SA:
Channel 1, 2, 3 Positive Input Select for Sample MUXA bit
In 12-bit mode (AD21B = 1), CH123SA is Unimplemented and is Read as ‘0’:
REGISTER 23-5:
AD1CHS123: ADC1 INPUT CHANNEL 1, 2, 3 SELECT REGISTER (CONTINUED)
Note 1:
AN0 through AN7 are repurposed when comparator and op amp functionality is enabled. See
Figure 23-1
to determine how enabling a particular op amp or comparator affects selection choices for Channels 1, 2
and 3.
and 3.
2:
The OAx input is used if the corresponding op amp is selected (OPMODE (CMxCON<10>) = 1);
otherwise, the ANx input is used.
otherwise, the ANx input is used.
Value
ADC Channel
CH1
CH2
CH3
1
(
)
OA1/AN3
OA2/AN0
OA3/AN6
0
(
,
OA2/AN0
AN1
AN2