Microchip Technology MA330031-2 Data Sheet
2011-2013 Microchip Technology Inc.
DS70000657H-page 381
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 27-2:
CONFIGURATION BITS DESCRIPTION
Bit Field
Description
GCP
General Segment Code-Protect bit
1
1
= User program memory is not code-protected
0
= Code protection is enabled for the entire program memory space
GWRP
General Segment Write-Protect bit
1
1
= User program memory is not write-protected
0
= User program memory is write-protected
IESO
Two-Speed Oscillator Start-up Enable bit
1
1
= Start up device with FRC, then automatically switch to the user-selected oscillator
source when ready
0
= Start up device with user-selected oscillator source
PWMLOCK
(
)
PWM Lock Enable bit
1
1
= Certain PWM registers may only be written after a key sequence
0
= PWM registers may be written without a key sequence
FNOSC<2:0>
Oscillator Selection bits
111
111
= Fast RC Oscillator with Divide-by-N (FRCDIVN)
110
= Fast RC Oscillator with Divide-by-16 (FRCDIV16)
101
= Low-Power RC Oscillator (LPRC)
100
= Reserved; do not use
011
= Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL)
010
= Primary Oscillator (XT, HS, EC)
001
= Fast RC Oscillator with Divide-by-N with PLL module (FRCPLL)
000
= Fast RC Oscillator (FRC)
FCKSM<1:0>
Clock Switching Mode bits
1x
1x
= Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01
= Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00
= Clock switching is enabled, Fail-Safe Clock Monitor is enabled
IOL1WAY
Peripheral Pin Select Configuration bit
1
1
= Allow only one reconfiguration
0
= Allow multiple reconfigurations
OSCIOFNC
OSC2 Pin Function bit (except in XT and HS modes)
1
1
= OSC2 is the clock output
0
= OSC2 is a general purpose digital I/O pin
POSCMD<1:0>
Primary Oscillator Mode Select bits
11
11
= Primary Oscillator is disabled
10
= HS Crystal Oscillator mode
01
= XT Crystal Oscillator mode
00
= EC (External Clock) mode
FWDTEN
Watchdog Timer Enable bit
1
1
= Watchdog Timer is always enabled (LPRC oscillator cannot be disabled. Clearing the
SWDTEN bit in the RCON register will have no effect.)
0
= Watchdog Timer is enabled/disabled by user software (LPRC can be disabled by clearing
the SWDTEN bit in the RCON register)
WINDIS
Watchdog Timer Window Enable bit
1
1
= Watchdog Timer in Non-Window mode
0
= Watchdog Timer in Window mode
PLLKEN
PLL Lock Enable bit
1
1
= PLL lock is enabled
0
= PLL lock is disabled
Note 1:
This bit is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices.
2:
When JTAGEN = 1, an internal pull-up resistor is enabled on the TMS pin. Erased devices default to
JTAGEN = 1. Applications requiring I/O pins in a high-impedance state (tri-state) in Reset should use pins
other than TMS for this purpose.
JTAGEN = 1. Applications requiring I/O pins in a high-impedance state (tri-state) in Reset should use pins
other than TMS for this purpose.