Microchip Technology MA330031-2 Data Sheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 382
2011-2013 Microchip Technology Inc.
WDTPRE
Watchdog Timer Prescaler bit
1
1
= 1:128
0
= 1:32
WDTPOST<3:0>
Watchdog Timer Postscaler bits
1111
1111
= 1:32,768
1110
= 1:16,384
•
•
•
0001
•
•
0001
= 1:2
0000
= 1:1
WDTWIN<1:0>
Watchdog Window Select bits
11
11
= WDT window is 25% of WDT period
10
= WDT window is 37.5% of WDT period
01
= WDT window is 50% of WDT period
00
= WDT window is 75% of WDT period
ALTI2C1
Alternate I2C1 pin
1
1
= I2C1 is mapped to the SDA1/SCL1 pins
0
= I2C1 is mapped to the ASDA1/ASCL1 pins
ALTI2C2
Alternate I2C2 pin
1
1
= I2C2 is mapped to the SDA2/SCL2 pins
0
= I2C2 is mapped to the ASDA2/ASCL2 pins
JTAGEN
)
JTAG Enable bit
1
1
= JTAG is enabled
0
= JTAG is disabled
ICS<1:0>
ICD Communication Channel Select bits
11
11
= Communicate on PGEC1 and PGED1
10
= Communicate on PGEC2 and PGED2
01
= Communicate on PGEC3 and PGED3
00
= Reserved, do not use
TABLE 27-2:
CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field
Description
Note 1:
This bit is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices.
2:
When JTAGEN = 1, an internal pull-up resistor is enabled on the TMS pin. Erased devices default to
JTAGEN = 1. Applications requiring I/O pins in a high-impedance state (tri-state) in Reset should use pins
other than TMS for this purpose.
JTAGEN = 1. Applications requiring I/O pins in a high-impedance state (tri-state) in Reset should use pins
other than TMS for this purpose.