Microchip Technology MA330031-2 Data Sheet

DS70000657H-page 384

 2011-2013 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X devices contain four
User ID Words, located at addresses, 0x800FF8
through 0x800FFE. The User ID Words can be used for
storing product information such as serial numbers,
system manufacturing dates, manufacturing lot
numbers and other application-specific information. 
The User ID Words register map is shown in

All of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/
MC20X devices power their core digital logic at a
nominal 1.8V. This can create a conflict for designs that
are required to operate at a higher typical voltage, such
as 3.3V. To simplify system design, all devices in the
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X family incorporate an on-
chip regulator that allows the device to run its core logic
from V

DD

.

The regulator provides power to the core from the other
V

DD

 pins. A low-ESR (less than 1 Ohm) capacitor (such

as tantalum or ceramic) must be connected to the V

CAP

pin (

). This helps to maintain the stability of

the regulator. The recommended value for the filter
capacitor is provided in 

 located in

. 

The Brown-out Reset (BOR) module is based on an
internal voltage reference circuit that monitors the reg-
ulated supply voltage, V

CAP

. The main purpose of the

BOR module is to generate a device Reset when a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (for
example, missing portions of the AC cycle waveform
due to bad power transmission lines or voltage sags
due to excessive current draw when a large inductive
load is turned on).
A BOR generates a Reset pulse, which resets the
device. The BOR selects the clock source, based on
the device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>).
If an oscillator mode is selected, the BOR activates the
Oscillator Start-up Timer (OST). The system clock is
held until OST expires. If the PLL is used, the clock is
held until the LOCK bit (OSCCON<5>) is ‘1’.
Concurrently, the PWRT Time-out (T

PWRT

) is applied

before the internal Reset is released. If T

PWRT

 = 0 and

a crystal oscillator is being used, then a nominal delay
of T

FSCM

 is applied. The total delay in this case is

T

FSCM

. Refer to Parameter 

 in 

 of

 for specific

T

FSCM

 values.

The BOR status bit (RCON<1>) is set to indicate that a
BOR has occurred. The BOR circuit continues to oper-
ate while in Sleep or Idle modes and resets the device
should V

DD

 fall below the BOR threshold voltage.

FUID0

0x800FF8

—

UID0

FUID1

0x800FFA

—

UID1

FUID2

0x800FFC

—

UID2

FUID3

0x800FFE

—

UID3

— = unimplemented, read as ‘1’.

It is important for the low-ESR capacitor to
be placed as close as possible to the V

CAP

pin.

These are typical operating voltages. 
Refer to 

 located in 

 for 

the full operating ranges of V

DD

 and V

CAP

. 

It is important for the low-ESR capacitor 
to be placed as close as possible to the 
V

CAP

 pin.

Typical V

CAP

 pin voltage = 1.8V when 

V

DD

 ≥ V

DDMIN

.

V

DD

V

CAP

V

SS

3.3V

C

EFC