Microchip Technology MA330031-2 Data Sheet
2011-2013 Microchip Technology Inc.
DS70000657H-page 509
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Revision C (December 2011)
This revision includes typographical and formatting
changes throughout the data sheet text.
In addition, where applicable, new sections were added
to each peripheral chapter that provide information and
links to related resources, as well as helpful tips. For
examples, see Section 20.1 “UART Helpful Tips”
and Section 3.6 “CPU Resources”.
changes throughout the data sheet text.
In addition, where applicable, new sections were added
to each peripheral chapter that provide information and
links to related resources, as well as helpful tips. For
examples, see Section 20.1 “UART Helpful Tips”
and Section 3.6 “CPU Resources”.
All occurrences of TLA were updated to VTLA
throughout the document, with the exception of the pin
diagrams (updated diagrams were not available at time
of publication).
A new chapter, Section 31.0 “DC and AC Device
Characteristics Graphs”
throughout the document, with the exception of the pin
diagrams (updated diagrams were not available at time
of publication).
A new chapter, Section 31.0 “DC and AC Device
Characteristics Graphs”
, was added.
All other major changes are referenced by their
respective section in
respective section in
.
TABLE A-2:
MAJOR SECTION UPDATES
Section Name
Update Description
“16-bit Microcontrollers
and Digital Signal
Controllers (up to
256-Kbyte Flash and
32-Kbyte SRAM) with High-
Speed PWM, Op amps, and
Advanced Analog”
and Digital Signal
Controllers (up to
256-Kbyte Flash and
32-Kbyte SRAM) with High-
Speed PWM, Op amps, and
Advanced Analog”
The content on the first page of this section was extensively reworked to provide the
reader with the key features and functionality of this device family in an “at-a-glance”
format.
reader with the key features and functionality of this device family in an “at-a-glance”
format.
Section 1.0 “Device
Overview”
Overview”
Updated the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, and
PIC24EPXXXGP/MC20X Block Diagram (see Figure 1-1), which now contains a CPU
block and a reference to the CPU diagram.
Updated the description and Note references in the Pinout I/O Descriptions for these
pins: C1IN2-, C2IN2-, C3IN2-, OA1OUT, OA2OUT, and OA3OUT (see Table 1-1).
PIC24EPXXXGP/MC20X Block Diagram (see Figure 1-1), which now contains a CPU
block and a reference to the CPU diagram.
Updated the description and Note references in the Pinout I/O Descriptions for these
pins: C1IN2-, C2IN2-, C3IN2-, OA1OUT, OA2OUT, and OA3OUT (see Table 1-1).
Section 2.0 “Guidelines for
Getting Started with 16-bit
Digital Signal Controllers
and Microcontrollers”
Getting Started with 16-bit
Digital Signal Controllers
and Microcontrollers”
Updated the Recommended Minimum Connection diagram (see Figure 2-1).
Section 3.0 “CPU”
Updated the dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, and
PIC24EPXXXGP/MC20X CPU Block Diagram (see Figure 3-1).
Updated the Status register definition in the Programmer’s Model (see Figure 3-2).
PIC24EPXXXGP/MC20X CPU Block Diagram (see Figure 3-1).
Updated the Status register definition in the Programmer’s Model (see Figure 3-2).
Section 4.0 “Memory
Organization”
Organization”
Updated the Data Memory Maps (see Figure 4-6 and Figure 4-11).
Removed the DCB<1:0> bits from the OC1CON2, OC2CON2, OC3CON2, and
OC4CON2 registers in the Output Compare 1 Through Output Compare 4 Register
Map (see Table 4-10).
Added the TRIG1 and TRGCON1 registers to the PWM Generator 1 Register Map
(see Table 4-13).
Added the TRIG2 and TRGCON2 registers to the PWM Generator 2 Register Map
(see Table 4-14).
Added the TRIG3 and TRGCON3 registers to the PWM Generator 3 Register Map
(see Table 4-15).
Updated the second note in Section 4.7.1 “Bit-Reversed Addressing
Implementation”
Removed the DCB<1:0> bits from the OC1CON2, OC2CON2, OC3CON2, and
OC4CON2 registers in the Output Compare 1 Through Output Compare 4 Register
Map (see Table 4-10).
Added the TRIG1 and TRGCON1 registers to the PWM Generator 1 Register Map
(see Table 4-13).
Added the TRIG2 and TRGCON2 registers to the PWM Generator 2 Register Map
(see Table 4-14).
Added the TRIG3 and TRGCON3 registers to the PWM Generator 3 Register Map
(see Table 4-15).
Updated the second note in Section 4.7.1 “Bit-Reversed Addressing
Implementation”
.
Section 8.0 “Direct Memory
Access (DMA)”
Access (DMA)”
Updated the DMA Controller diagram (see Figure 8-1).
Section 14.0 “Input
Capture”
Capture”
Updated the bit values for the ICx clock source of the ICTSEL<12:10> bits in the
ICxCON1 register (see Register 14-1).
ICxCON1 register (see Register 14-1).
Section 15.0 “Output
Compare”
Compare”
Updated the bit values for the OCx clock source of the OCTSEL<2:0> bits in the
OCxCON1 register (see Register 15-1).
Removed the DCB<1:0> bits from the Output Compare x Control Register 2 (see
Register 15-2).
OCxCON1 register (see Register 15-1).
Removed the DCB<1:0> bits from the Output Compare x Control Register 2 (see
Register 15-2).