Microchip Technology MA330031-2 Data Sheet
2011-2013 Microchip Technology Inc.
DS70000657H-page 507
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
APPENDIX A:
REVISION HISTORY
Revision A (April 2011)
This is the initial released version of the document.
Revision B (July 2011)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
All other major changes are referenced by their
respective section in
formatting changes throughout the data sheet text.
All other major changes are referenced by their
respective section in
TABLE A-1:
MAJOR SECTION UPDATES
Section Name
Update Description
“High-Performance, 16-bit
Digital Signal Controllers
and Microcontrollers”
Digital Signal Controllers
and Microcontrollers”
Changed all pin diagrams references of VLAP to TLA.
Section 4.0 “Memory
Organization”
Organization”
Updated the All Resets values for CLKDIV and PLLFBD in the System Control
Register Map (see Table 4-35).
Register Map (see Table 4-35).
Section 5.0 “Flash Program
Memory”
Memory”
Updated “one word” to “two words” in the first paragraph of Section 5.2 “RTSP
Operation”
Operation”
.
Section 9.0 “Oscillator
Configuration”
Configuration”
Updated the PLL Block Diagram (see Figure 9-2).
Updated the Oscillator Mode, Fast RC Oscillator (FRC) with divide-by-N and PLL
(FRCPLL), by changing (FRCDIVN + PLL) to (FRCPLL).
Changed (FRCDIVN + PLL) to (FRCPLL) for COSC<2:0> = 001 and
NOSC<2:0> = 001 in the Oscillator Control Register (see Register 9-1).
Changed the POR value from 0 to 1 for the DOZE<1:0> bits, from 1 to 0 for the
FRCDIV<0> bit, and from 0 to 1 for the PLLPOST<0> bit; Updated the default
definitions for the DOZE<2:0> and FRCDIV<2:0> bits and updated all bit definitions
for the PLLPOST<1:0> bits in the Clock Divisor Register (see Register 9-2).
Changed the POR value from 0 to 1 for the PLLDIV<5:4> bits and updated the default
definitions for all PLLDIV<8:0> bits in the PLL Feedback Division Register (see
Register 9-2).
Updated the Oscillator Mode, Fast RC Oscillator (FRC) with divide-by-N and PLL
(FRCPLL), by changing (FRCDIVN + PLL) to (FRCPLL).
Changed (FRCDIVN + PLL) to (FRCPLL) for COSC<2:0> = 001 and
NOSC<2:0> = 001 in the Oscillator Control Register (see Register 9-1).
Changed the POR value from 0 to 1 for the DOZE<1:0> bits, from 1 to 0 for the
FRCDIV<0> bit, and from 0 to 1 for the PLLPOST<0> bit; Updated the default
definitions for the DOZE<2:0> and FRCDIV<2:0> bits and updated all bit definitions
for the PLLPOST<1:0> bits in the Clock Divisor Register (see Register 9-2).
Changed the POR value from 0 to 1 for the PLLDIV<5:4> bits and updated the default
definitions for all PLLDIV<8:0> bits in the PLL Feedback Division Register (see
Register 9-2).
Section 22.0 “Charge Time
Measurement Unit (CTMU)”
Measurement Unit (CTMU)”
Updated the bit definitions for the IRNG<1:0> bits in the CTMU Current Control
Register (see Register 22-3).
Register (see Register 22-3).
Section 25.0 “Op amp/
Comparator Module”
Comparator Module”
Updated the voltage reference block diagrams (see Figure 25-1 and Figure 25-2).