Microchip Technology TDGL003 - chipKIT Max32 Development Board TDGL003 TDGL003 Data Sheet
Product codes
TDGL003
PIC32MX3XX/4XX
DS61143H-page 100
© 2011 Microchip Technology Inc.
FIGURE 11-1:
PIC32MX3XX/4XX FAMILY USB INTERFACE DIAGRAM
OSC1
OSC2
Primary Oscillator
8 MHz Typical
FRC
Oscillator
TUN<5:0>
(4)
PLL
48 MHz USB Clock
(7)
Div x
UPLLEN
(6)
(PB out)
(1)
UFRCEN
(3)
(P
OSC
)
UPLLIDIV
(6)
UF
IN
(5)
Div 2
V
USB
D+
(2)
D-
(2)
ID
(8)
V
BUS
Transceiver
SIE
V
BUSON
(8)
Comparators
USB
SRP Charge
SRP Discharge
Registers
and
Control
Interface
Transceiver Power 3.3V
To Clock Generator for Core and Peripherals
Sleep or Idle
Sleep
USBEN
USB Suspend
CPU Clock Not P
OSC
USB Module
Voltage
System
RAM
USB Suspend
Full Speed Pull-up
Host Pull-down
Low Speed Pull-up
Host Pull-down
ID Pull-up
DMA
Note
1:
PB clock is only available on this pin for select EC modes.
2:
Pins can be used as digital inputs when USB is not enabled.
3:
This bit field is contained in the OSCCON register.
4:
This bit field is contained in the OSCTRM register.
5:
USB PLL UF
IN
requirements: 4 MHz.
6:
This bit field is contained in the DEVCFG2 register.
7:
A 48 MHz clock is required for proper USB operation.
8:
Pins can be used as GPIO when the USB module is disabled.