Microchip Technology GPIODM-KPLCD Data Sheet
PIC18F2455/2550/4455/4550
DS39632E-page 12
© 2009 Microchip Technology Inc.
TABLE 1-2:
PIC18F2455/2550 PINOUT I/O DESCRIPTIONS
Pin Name
Pin
Number Pin
Type
Buffer
Type
Description
PDIP,
SOIC
SOIC
MCLR/V
PP
/RE3
MCLR
V
PP
RE3
1
I
P
I
ST
ST
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Digital input.
Reset to the device.
Programming voltage input.
Digital input.
OSC1/CLKI
OSC1
CLKI
CLKI
9
I
I
I
Analog
Analog
Analog
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
External clock source input. Always associated with pin
function OSC1. (See OSC2/CLKO pin.)
External clock source input. Always associated with pin
function OSC1. (See OSC2/CLKO pin.)
OSC2/CLKO/RA6
OSC2
CLKO
RA6
10
O
O
I/O
—
—
TTL
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode.
In select modes, OSC2 pin outputs CLKO which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin.
Crystal Oscillator mode.
In select modes, OSC2 pin outputs CLKO which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I
= Input
O
= Output
P
= Power
Note 1:
Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2:
Default assignment for CCP2 when CCP2MX Configuration bit is set.