Data SheetTable of Contents1.0 Device Overview52.0 Electrical Characteristics233.0 Packaging Information33Size: 649 KBPages: 44Language: EnglishOpen manual
Data SheetTable of Contents1.0 Device Overview31.1 Pin Descriptions41.2 Power-on Reset (POR)51.3 Serial Interface51.4 Hardware Address Decoder81.5 GPIO Port91.6 Configuration and Control Registers101.7 Interrupt Logic242.0 Electrical Characteristics272.1 DC Characteristics283.0 Packaging Information373.1 Package Marking Information37Size: 916 KBPages: 48Language: EnglishOpen manual
User ManualTable of ContentsPreface5Introduction5Document Layout5Conventions Used in this Guide6Recommended Reading6The Microchip Web Site7Customer Support7Document Revision History7Chapter 1. Product Overview91.1 Introduction91.2 What is the GPIO Expander Keypad and LCD Demo Board?91.3 What The GPIO Expander Keypad and LCD Demo Board Kit Includes9Chapter 2. Installation and Operation112.1 Introduction112.2 Features112.3 Getting Started122.4 GPIO Expander Keypad and LCD Demo Board Description132.4.1 Major Board Components132.5 Firmware Description14Appendix A. Schematics and Board Layouts19A.1 Introduction19A.2 Board Schematic - Page 120A.3 Board Schematic - Page 221A.4 Board Schematic - Page 322A.5 Board - Top Layer (with Silk screen)23A.6 Board - Bottom Layer23Appendix B. Bill Of Materials (BOM)25Worldwide Sales and Service28Size: 784 KBPages: 28Language: EnglishOpen manual
Data SheetTable of ContentsUniversal Serial Bus Features:3Power-Managed Modes:3Flexible Oscillator Structure:3Peripheral Highlights:3Special Microcontroller Features:3Pin Diagrams4Pin Diagrams (Continued)5Table of Contents6Most Current Data Sheet7Errata7Customer Notification System71.0 Device Overview91.1 New Core Features91.1.1 nanoWatt Technology91.1.2 Universal Serial Bus (USB)91.1.3 Multiple Oscillator Options and Features91.2 Other Special Features101.3 Details on Individual Family Members10TABLE 1-1: Device Features11FIGURE 1-1: PIC18F2455/2550 (28-Pin) Block Diagram12FIGURE 1-2: PIC18F4455/4550 (40/44-Pin) Block Diagram13TABLE 1-2: PIC18f2455/2550 Pinout I/O Descriptions14TABLE 1-3: PIC18F4455/4550 Pinout I/O Descriptions182.0 Oscillator Configurations252.1 Overview252.1.1 Oscillator Control252.2 Oscillator Types252.2.1 Oscillator Modes and USB Operation25FIGURE 2-1: PIC18F2455/2550/4455/4550 Clock Diagram262.2.2 Crystal Oscillator/Ceramic Resonators27FIGURE 2-2: Crystal/Ceramic Resonator Operation (XT, HS or HSPLL Configuration)27TABLE 2-1: Capacitor Selection for Ceramic Resonators27TABLE 2-2: Capacitor Selection for Crystal Oscillator28FIGURE 2-3: External Clock Input Operation (HS Osc Configuration)282.2.3 External Clock Input28FIGURE 2-4: External Clock Input Operation (EC and ECPLL Configuration)28FIGURE 2-5: External Clock Input Operation (ECIO and ECPIO Configuration)282.2.4 PLL Frequency Multiplier29FIGURE 2-6: PLL Block Diagram (HS Mode)292.2.5 Internal Oscillator Block29Register 2-1: OSCTUNE: Oscillator Tuning Register302.3 Oscillator Settings for USB322.3.1 Low-Speed Operation322.3.2 Running Different USB and Microcontroller Clocks32TABLE 2-3: Oscillator Configuration Options for USB Operation322.4 Clock Sources and Oscillator Switching342.4.1 Oscillator Control Register342.4.2 Oscillator Transitions35Register 2-2: OSCCON: Oscillator Control Register352.5 Effects of Power-Managed Modes on the Various Clock Sources362.6 Power-up Delays36TABLE 2-4: OSC1 and OSC2 Pin States in Sleep Mode363.0 Power-Managed Modes373.1 Selecting Power-Managed Modes373.1.1 Clock Sources373.1.2 Entering Power-Managed Modes37TABLE 3-1: Power-Managed Modes373.1.3 Clock Transitions and Status Indicators383.1.4 Multiple Sleep Commands38EXAMPLE 3-1: Executing Back to Back SLEEP Instructions383.2 Run Modes383.2.1 PRI_RUN Mode383.2.2 SEC_RUN Mode38FIGURE 3-1: Transition Timing for Entry to SEC_RUN Mode39FIGURE 3-2: Transition Timing From SEC_RUN Mode to PRI_RUN Mode (HSPLL)393.2.3 RC_RUN Mode40FIGURE 3-3: Transition Timing to RC_RUN Mode41FIGURE 3-4: Transition Timing From RC_RUN Mode to PRI_RUN Mode413.3 Sleep Mode423.4 Idle Modes42FIGURE 3-5: Transition Timing for Entry to Sleep Mode42FIGURE 3-6: Transition Timing for Wake From Sleep (HSPLL)423.4.1 PRI_IDLE Mode433.4.2 SEC_IDLE Mode43FIGURE 3-7: Transition Timing for Entry to Idle Mode43FIGURE 3-8: Transition Timing for Wake From Idle to Run Mode433.4.3 RC_IDLE Mode443.5 Exiting Idle and Sleep Modes443.5.1 Exit By Interrupt443.5.2 Exit By WDT Time-out443.5.3 Exit By Reset443.5.4 Exit Without an Oscillator Start-up Delay45TABLE 3-2: Exit Delay on Wake-up By Reset From Sleep Mode or Any Idle Mode (By Clock Sources)454.0 Reset474.1 RCON Register47FIGURE 4-1: Simplified Block Diagram of On-Chip Reset Circuit47Register 4-1: RCON: Reset Control Register484.2 Master Clear Reset (MCLR)494.3 Power-on Reset (POR)49FIGURE 4-2: External Power-on Reset Circuit (for Slow Vdd Power-up)494.4 Brown-out Reset (BOR)504.4.1 Software Enabled BOR504.4.2 Detecting BOR504.4.3 Disabling BOR in Sleep Mode50TABLE 4-1: BOR Configurations504.5 Device Reset Timers514.5.1 Power-up Timer (PWRT)514.5.2 Oscillator Start-up Timer (OST)514.5.3 PLL Lock Time-out514.5.4 Time-out Sequence51TABLE 4-2: Time-out in Various Situations51FIGURE 4-3: Time-out Sequence on Power-up (MCLR Tied to Vdd, Vdd Rise < Tpwrt)52FIGURE 4-4: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 152FIGURE 4-5: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 252FIGURE 4-6: Slow Rise Time (MCLR Tied to Vdd, Vdd Rise > Tpwrt)53FIGURE 4-7: Time-out Sequence on POR w/PLL Enabled (MCLR Tied to Vdd)534.6 Reset State of Registers54TABLE 4-3: Status Bits, Their Significance and the Initialization Condition for RCON Register54TABLE 4-4: Initialization Conditions for All Registers555.0 Memory Organization615.1 Program Memory Organization61FIGURE 5-1: Program Memory Map and Stack615.1.1 Program Counter625.1.2 Return Address Stack62FIGURE 5-2: Return Address Stack and Associated Registers62Register 5-1: STKPTR: Stack Pointer Register635.1.3 Fast Register Stack64EXAMPLE 5-1: Fast Register Stack Code Example645.1.4 Look-up Tables in Program Memory64EXAMPLE 5-2: Computed GOTO Using an Offset Value645.2 PIC18 Instruction Cycle655.2.1 Clocking Scheme655.2.2 Instruction Flow/Pipelining65FIGURE 5-3: Clock/ Instruction Cycle65EXAMPLE 5-3: Instruction Pipeline Flow655.2.3 Instructions in Program Memory66FIGURE 5-4: Instructions in Program Memory665.2.4 Two-Word Instructions66EXAMPLE 5-4: Two-Word Instructions665.3 Data Memory Organization675.3.1 USB RAM675.3.2 Bank Select Register (BSR)67FIGURE 5-5: Data Memory Map68FIGURE 5-6: Use of the Bank Select Register (Direct Addressing)695.3.3 Access Bank695.3.4 General Purpose Register File695.3.5 Special Function Registers70TABLE 5-1: Special Function Register Map70TABLE 5-2: Register File Summary715.3.6 Status Register75Register 5-2: Status Register755.4 Data Addressing Modes765.4.1 Inherent and Literal Addressing765.4.2 Direct Addressing765.4.3 Indirect Addressing76EXAMPLE 5-5: How to Clear RAM (Bank 1) Using Indirect Addressing76FIGURE 5-7: Indirect Addressing775.5 Program Memory and the Extended Instruction Set795.6 Data Memory and the Extended Instruction Set795.6.1 Indexed Addressing with Literal Offset795.6.2 Instructions Affected By Indexed Literal Offset Mode79FIGURE 5-8: Comparing Addressing Options for Bit-Oriented and Byte-Oriented Instructions (Extended Instruction Set Enabled)805.6.3 Mapping the Access Bank in Indexed Literal Offset Mode815.6.4 BSR in Indexed Literal Offset Mode81FIGURE 5-9: Remapping the Access Bank with Indexed Literal Offset Addressing816.0 Flash Program Memory836.1 Table Reads and Table Writes83FIGURE 6-1: Table Read Operation83FIGURE 6-2: Table Write Operation846.2 Control Registers846.2.1 EECON1 and EECON2 Registers84Register 6-1: EECON1: Data EEPROM Control Register 1856.2.2 Table Latch Register (TABLAT)866.2.3 Table Pointer Register (TBLPTR)866.2.4 Table Pointer Boundaries86TABLE 6-1: Table Pointer Operations with TBLRD and TBLWT Instructions86FIGURE 6-3: Table Pointer Boundaries Based on Operation866.3 Reading the Flash Program Memory87FIGURE 6-4: Reads From Flash Program Memory87EXAMPLE 6-1: Reading a Flash Program Memory Word876.4 Erasing Flash Program Memory886.4.1 Flash Program Memory Erase Sequence88EXAMPLE 6-2: Erasing a Flash Program Memory Row886.5 Writing to Flash Program Memory89FIGURE 6-5: Table Writes to Flash Program Memory896.5.1 Flash Program Memory Write Sequence89EXAMPLE 6-3: Writing to Flash Program Memory90EXAMPLE 6-3: Writing to Flash Program Memory (Continued)916.5.2 Write Verify916.5.3 Unexpected Termination of Write Operation916.5.4 Protection Against Spurious Writes916.6 Flash Program Operation During Code Protection91TABLE 6-2: Registers Associated with Program Flash Memory917.0 Data EEPROM Memory937.1 EECON1 and EECON2 Registers93Register 7-1: EECON1: Data EEPROM Control Register 1947.2 Reading the Data EEPROM Memory957.3 Writing to the Data EEPROM Memory957.4 Write Verify95EXAMPLE 7-1: Data EEPROM Read95EXAMPLE 7-2: Data EEPROM Write957.5 Operation During Code-Protect967.6 Protection Against Spurious Write967.7 Using the Data EEPROM96EXAMPLE 7-3: Data EEPROM Refresh Routine96TABLE 7-1: Registers Associated with Data EEPROM Memory978.0 8 x 8 Hardware Multiplier998.1 Introduction998.2 Operation99EXAMPLE 8-1: 8 x 8 Unsigned Multiply Routine99EXAMPLE 8-2: 8 x 8 Signed Multiply Routine99TABLE 8-1: Performance Comparison for Various Multiply Operations99EQUATION 8-1: 16 x 16 Unsigned Multiplication Algorithm100EXAMPLE 8-3: 16 x 16 Unsigned Multiply Routine100EQUATION 8-2: 16 x 16 Signed Multiplication Algorithm100EXAMPLE 8-4: 16 x 16 Signed Multiply Routine1009.0 Interrupts1019.1 USB Interrupts101FIGURE 9-1: Interrupt Logic1029.2 INTCON Registers103Register 9-1: INTCON: Interrupt Control Register103Register 9-2: INTCON2: Interrupt Control Register 2104Register 9-3: INTCON3: Interrupt Control Register 31059.3 PIR Registers106Register 9-4: PIR1: Peripheral Interrupt Request (Flag) Register 1106Register 9-5: PIR2: Peripheral Interrupt Request (Flag) Register 21079.4 PIE Registers108Register 9-6: PIE1: Peripheral Interrupt Enable Register 1108Register 9-7: PIE2: Peripheral Interrupt Enable Register 21099.5 IPR Registers110Register 9-8: IPR1: Peripheral Interrupt Priority Register 1110Register 9-9: IPR2: Peripheral Interrupt Priority Register 21119.6 RCON Register112Register 9-10: RCON: Reset Control Register1129.7 INTx Pin Interrupts1139.8 TMR0 Interrupt1139.9 PORTB Interrupt-on-Change1139.10 Context Saving During Interrupts113EXAMPLE 9-1: Saving Status, WREG and BSR Registers in RAM11310.0 I/O Ports115FIGURE 10-1: Generic I/O Port Operation11510.1 PORTA, TRISA and LATA Registers115EXAMPLE 10-1: Initializing PORTA115TABLE 10-1: PORTA I/O Summary116TABLE 10-2: Summary of Registers Associated with PORTA11710.2 PORTB, TRISB and LATB Registers118EXAMPLE 10-2: Initializing PORTB118TABLE 10-3: PORTB I/O Summary119TABLE 10-4: Summary of Registers Associated with PORTB12010.3 PORTC, TRISC and LATC Registers121EXAMPLE 10-3: Initializing PORTC121TABLE 10-5: PORTC I/O Summary122TABLE 10-6: Summary of Registers Associated with PORTC12310.4 PORTD, TRISD and LATD Registers124EXAMPLE 10-4: Initializing PORTD124TABLE 10-7: PORTD I/O Summary125TABLE 10-8: Summary of Registers Associated with PORTD12610.5 PORTE, TRISE and LATE Registers127EXAMPLE 10-5: Initializing PORTE12710.5.1 PORTE in 28-Pin Devices127Register 10-1: PORTE Register127TABLE 10-9: PORTE I/O Summary128TABLE 10-10: Summary of Registers Associated with PORTE12811.0 Timer0 Module129Register 11-1: T0CON: Timer0 Control Register12911.1 Timer0 Operation13011.2 Timer0 Reads and Writes in 16-Bit Mode130FIGURE 11-1: Timer0 Block Diagram (8-bit Mode)130FIGURE 11-2: Timer0 Block Diagram (16-bit Mode)13011.3 Prescaler13111.3.1 Switching Prescaler Assignment13111.4 Timer0 Interrupt131TABLE 11-1: Registers Associated with Timer013112.0 Timer1 Module133Register 12-1: T1CON: Timer1 Control Register13312.1 Timer1 Operation134FIGURE 12-1: Timer1 Block Diagram134FIGURE 12-2: Timer1 Block Diagram (16-bit Read/Write Mode)13412.2 Timer1 16-Bit Read/Write Mode13512.3 Timer1 Oscillator135FIGURE 12-3: External Components for the Timer1 LP Oscillator135TABLE 12-1: Capacitor Selection for the Timer Oscillator(2,3,4)13512.3.1 Using Timer1 as a Clock Source13512.3.2 Low-Power Timer1 Option13512.3.3 Timer1 Oscillator Layout Considerations136FIGURE 12-4: Oscillator Circuit with Grounded Guard Ring13612.4 Timer1 Interrupt13612.5 Resetting Timer1 Using the CCP Special Event Trigger13612.6 Using Timer1 as a Real-Time Clock13612.7 Considerations in Asynchronous Counter Mode137EXAMPLE 12-1: Implementing a Real-Time Clock Using a Timer1 Interrupt Service137TABLE 12-2: Registers Associated with Timer1 as a Timer/Counter13813.0 Timer2 Module13913.1 Timer2 Operation139Register 13-1: T2CON: Timer2 Control Register13913.2 Timer2 Interrupt14013.3 TMR2 Output140FIGURE 13-1: Timer2 Block Diagram140TABLE 13-1: Registers Associated with Timer2 as a Timer/Counter14014.0 Timer3 Module141Register 14-1: T3CON: Timer3 Control Register14114.1 Timer3 Operation142FIGURE 14-1: Timer3 Block Diagram142FIGURE 14-2: Timer3 Block Diagram (16-bit Read/Write Mode)14214.2 Timer3 16-Bit Read/Write Mode14314.3 Using the Timer1 Oscillator as the Timer3 Clock Source14314.4 Timer3 Interrupt14314.5 Resetting Timer3 Using the CCP Special Event Trigger143TABLE 14-1: Registers Associated with Timer3 as a Timer/Counter14315.0 Capture/Compare/PWM (CCP) Modules145Register 15-1: CCPxCON: Standard CCPx Control Register14515.1 CCP Module Configuration14615.1.1 CCP Modules and Timer Resources146TABLE 15-1: CCP Mode – Timer Resource14615.1.2 CCP2 Pin Assignment146TABLE 15-2: Interactions Between CCP1 and CCP2 for Timer Resources14615.2 Capture Mode14715.2.1 CCP Pin Configuration14715.2.2 Timer1/Timer3 Mode Selection14715.2.3 Software Interrupt14715.2.4 CCP Prescaler147EXAMPLE 15-1: Changing Between Capture Prescalers (CCP2 Shown)147FIGURE 15-1: Capture Mode Operation Block Diagram14715.3 Compare Mode14815.3.1 CCP Pin Configuration14815.3.2 Timer1/Timer3 Mode Selection14815.3.3 Software Interrupt Mode14815.3.4 Special Event Trigger148FIGURE 15-2: Compare Mode Operation Block Diagram148TABLE 15-3: Registers Associated with Capture, Compare, Timer1 and Timer314915.4 PWM Mode150FIGURE 15-3: Simplified PWM Block Diagram150FIGURE 15-4: PWM Output15015.4.1 PWM Period150EQUATION 15-1:15015.4.2 PWM Duty Cycle150EQUATION 15-2:150EQUATION 15-3:151TABLE 15-4: Example PWM Frequencies and Resolutions at 40 MHz15115.4.3 PWM Auto-Shutdown (CCP1 Only)15115.4.4 Setup for PWM Operation151TABLE 15-5: Registers Associated with PWM and Timer215216.0 Enhanced Capture/Compare/PWM (ECCP) Module153Register 16-1: CCP1CON: ECCP Control Register (40/44-Pin Devices)15316.1 ECCP Outputs and Configuration15416.1.1 ECCP Modules and Timer Resources15416.2 Capture and Compare Modes15416.2.1 Special Event Trigger15416.3 Standard PWM Mode154TABLE 16-1: Pin Assignments for Various ECCP1 Modes15416.4 Enhanced PWM Mode15516.4.1 PWM Period155EQUATION 16-1:155FIGURE 16-1: Simplified Block Diagram of the Enhanced PWM Module15516.4.2 PWM Duty Cycle156EQUATION 16-2:156EQUATION 16-3:15616.4.3 PWM Output Configurations156TABLE 16-2: Example PWM Frequencies and Resolutions at 40 MHz156FIGURE 16-2: PWM Output Relationships (Active-High State)157FIGURE 16-3: PWM Output Relationships (Active-Low State)15716.4.4 Half-Bridge Mode158FIGURE 16-4: Half-Bridge PWM Output158FIGURE 16-5: Examples of Half-Bridge Output Mode Applications15816.4.5 Full-Bridge Mode159FIGURE 16-6: Full-Bridge PWM Output159FIGURE 16-7: Example of Full-Bridge Application160FIGURE 16-8: PWM Direction Change161FIGURE 16-9: PWM Direction Change at Near 100% Duty Cycle16116.4.6 Programmable Dead-Band Delay16216.4.7 Enhanced PWM Auto-Shutdown162Register 16-2: ECCP1DEL: PWM Dead-Band Delay Register162Register 16-3: ECCP1AS: Enhanced Capture/Compare/PWM Auto-Shutdown Control Register16316.4.8 Start-up Considerations164FIGURE 16-10: PWM Auto-Shutdown (PRSEN = 1, Auto-Restart Enabled)164FIGURE 16-11: PWM Auto-Shutdown (PRSEN = 0, Auto-Restart Disabled)16416.4.9 Setup for PWM Operation16516.4.10 Operation in Power-Managed Modes16516.4.11 Effects of a Reset165TABLE 16-3: Registers Associated with ECCP Module And Timer1 to Timer316617.0 Universal Serial Bus (USB)16717.1 Overview of the USB Peripheral167FIGURE 17-1: USB Peripheral and Options16717.2 USB Status and Control16817.2.1 USB Control Register (UCON)168Register 17-1: UCON: USB Control Register16817.2.2 USB Configuration Register (UCFG)169FIGURE 17-2: Typical External Transceiver with Isolation169Register 17-2: UCFG: USB Configuration Register170TABLE 17-1: Differential Outputs to Transceiver171TABLE 17-2: Single-Ended Inputs From Transceiver171FIGURE 17-3: External Circuitry17117.2.3 USB Status Register (USTAT)172FIGURE 17-4: USTAT FIFO172Register 17-3: USTAT: USB Status Register17317.2.4 USB Endpoint Control174Register 17-4: UEPn: USB Endpoint n Control Register (UEP0 Through UEP15)17417.2.5 USB Address Register (UADDR)17517.2.6 USB Frame Number Registers (UFRMH:UFRML)17517.3 USB RAM175FIGURE 17-5: Implementation of USB RAM in Data Memory Space17517.4 Buffer Descriptors and the Buffer Descriptor Table17617.4.1 BD Status and Configuration176FIGURE 17-6: Example of a Buffer Descriptor176TABLE 17-3: Effect of DTSEN Bit on Odd/Even (DATA0/DATA1) Packet Reception177Register 17-5: BDnSTAT: Buffer Descriptor n Status Register (BD0STAT Through BD63STAT), CPU Mode (Data is Written to the Side)17817.4.2 BD Byte Count17917.4.3 BD Address Validation179Register 17-6: BDnSTAT: Buffer Descriptor n Status Register (BD0STAT Through BD63STAT), SIE Mode (Data Returned By the Side to the Microcontroller)17917.4.4 Ping-Pong Buffering180FIGURE 17-7: Buffer Descriptor Table Mapping for Buffering Modes180TABLE 17-4: Assignment of Buffer Descriptors for the Different Buffering Modes181TABLE 17-5: Summary of USB Buffer Descriptor Table Registers18117.5 USB Interrupts182FIGURE 17-8: USB Interrupt Logic Funnel182FIGURE 17-9: Example of a USB Transaction and Interrupt Events18217.5.1 USB Interrupt Status Register (UIR)183Register 17-7: UIR: USB Interrupt Status Register183EXAMPLE 17-1: Clearing ACTVIF Bit (UIR<2>)18417.5.2 USB Interrupt Enable Register (UIE)185Register 17-8: UIE: USB Interrupt Enable Register18517.5.3 USB Error Interrupt Status Register (UEIR)186Register 17-9: UEIR: USB Error Interrupt Status Register18617.5.4 USB Error Interrupt Enable Register (UEIE)187Register 17-10: UEIE: USB Error Interrupt Enable Register18717.6 USB Power Modes18817.6.1 Bus Power Only188FIGURE 17-10: Bus Power Only18817.6.2 Self-Power Only188FIGURE 17-11: Self-power Only18817.6.3 Dual Power with Self-Power Dominance188FIGURE 17-12: Dual Power Example18817.7 Streaming Parallel Port18917.8 Oscillator18917.9 USB Firmware and DriversTABLE 17-6: Registers Associated with USB Module Operation(1)18917.10 Overview of USB19117.10.1 Layered Framework19117.10.2 Frames19117.10.3 Transfers19117.10.4 Power191FIGURE 17-13: USB Layers19117.10.5 Enumeration19217.10.6 Descriptors19217.10.7 Bus Speed19217.10.8 Class Specifications and Drivers19218.0 Streaming Parallel Port193FIGURE 18-1: SPP Data Path19318.1 SPP Configuration19318.1.1 Enabling the SPP193Register 18-1: SPPCON: SPP Control Register193Register 18-2: SPPCFG: SPP Configuration Register19418.1.2 Clocking Data19418.1.3 Wait States19418.1.4 SPP Pull-ups194FIGURE 18-2: Timing for Microcontroller Write Address, Write Data and Read Data (No Wait States)195FIGURE 18-3: Timing for USB Write Address and Data (4 Wait States)195FIGURE 18-4: Timing for USB Write Address and Read Data (4 Wait States)19518.2 Setup for USB Control19618.3 Setup for Microcontroller Control19618.3.1 SPP Interrupts19618.3.2 Writing to the SPP196FIGURE 18-5: Transfer of Data Between USB SIE and SPP19618.3.3 Reading From the SPP197Register 18-3: SPPEPS: SPP Endpoint Address and Status Register197TABLE 18-1: Registers Associated with the Streaming Parallel Port19819.0 Master Synchronous Serial Port (MSSP) Module19919.1 Master SSP (MSSP) Module Overview19919.2 Control Registers19919.3 SPI Mode199FIGURE 19-1: MSSP Block Diagram (SPI Mode)19919.3.1 Registers200Register 19-1: SSPSTAT: MSSP Status Register (SPI Mode)200Register 19-2: SSPCON1: MSSP Control Register 1 (SPI Mode)20119.3.2 Operation202EXAMPLE 19-1: Loading the SSPBUF (SSPSR) Register20219.3.3 Enabling SPI I/O20319.3.4 Typical Connection203FIGURE 19-2: SPI Master/Slave Connection20319.3.5 Master Mode204EXAMPLE 19-2: LOADING SSPBUF WITH THE TIMER2/2 CLOCK MODE204FIGURE 19-3: SPI Mode Waveform (Master Mode)20519.3.6 Slave Mode20619.3.7 Slave Select Synchronization206FIGURE 19-4: Slave Synchronization Waveform206FIGURE 19-5: SPI Mode Waveform (Slave Mode with CKE = 0)207FIGURE 19-6: SPI Mode Waveform (Slave Mode with CKE = 1)20719.3.8 Operation in Power-Managed Modes20819.3.9 Effects of a Reset20819.3.10 Bus Mode Compatibility208TABLE 19-1: SPI Bus Modes208TABLE 19-2: Registers Associated with SPI Operation20819.4 I2C Mode209FIGURE 19-7: MSSP Block Diagram (I2C™ Mode)20919.4.1 Registers209Register 19-3: SSPSTAT: MSSP Status Register (I2C™ Mode)210Register 19-4: SSPCON1: MSSP Control Register 1 (I2C™ Mode)211Register 19-5: SSPCON2: MSSP Control Register 2 (I2C™ Master Mode)212Register 19-6: SSPCON2: MSSP Control Register 2 (I2C™ Slave Mode)21319.4.2 Operation21419.4.3 Slave Mode214EXAMPLE 19-3: Address Masking Examples215FIGURE 19-8: I2C™ Slave Mode Timing with SEN = 0 (Reception, 7-Bit Address)217FIGURE 19-9: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01011 (Reception, 7-bit Address)218FIGURE 19-10: I2C™ Slave Mode Timing (Transmission, 7-Bit Address)219FIGURE 19-11: I2C™ Slave Mode Timing with SEN = 0 (Reception, 10-Bit Address)220FIGURE 19-12: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01001 (Reception, 10-bit Address)221FIGURE 19-13: I2C™ Slave Mode Timing (Transmission, 10-bit Address)22219.4.4 Clock Stretching223FIGURE 19-14: Clock Synchronization Timing224FIGURE 19-15: I2C™ Slave Mode Timing with SEN = 1 (Reception, 7-Bit Address)225FIGURE 19-16: I2C™ Slave Mode Timing with SEN = 1 (Reception, 10-Bit Address)22619.4.5 General Call Address Support227FIGURE 19-17: Slave Mode General Call Address Sequence (7 or 10-Bit Addressing Mode)22719.4.6 Master Mode228FIGURE 19-18: MSSP Block Diagram (I2C™ Master Mode)22819.4.7 Baud Rate230FIGURE 19-19: Baud Rate Generator Block Diagram230TABLE 19-3: I2C™ Clock Rate w/BRG230FIGURE 19-20: Baud Rate Generator Timing with Clock Arbitration23119.4.8 I2C Master Mode Start Condition Timing232FIGURE 19-21: First Start Bit Timing23219.4.9 I2C Master Mode Repeated Start Condition Timing233FIGURE 19-22: Repeated Start Condition Waveform23319.4.10 I2C Master Mode Transmission23419.4.11 I2C Master Mode Reception234FIGURE 19-23: I2C™ Master Mode Waveform (Transmission, 7 or 10-Bit Address)235FIGURE 19-24: I2C™ Master Mode Waveform (Reception, 7-Bit Address)23619.4.12 Acknowledge Sequence Timing23719.4.13 Stop Condition Timing237FIGURE 19-25: Acknowledge Sequence Waveform237FIGURE 19-26: Stop Condition Receive or Transmit Mode23719.4.14 Sleep Operation23819.4.15 EffectS of a Reset23819.4.16 Multi-Master Mode23819.4.17 Multi -Master Communication, Bus Collision and Bus Arbitration238FIGURE 19-27: Bus Collision Timing for Transmit and Acknowledge238FIGURE 19-28: Bus Collision During Start Condition (SDA Only)239FIGURE 19-29: Bus Collision During Start Condition (SCL = 0)240FIGURE 19-30: BRG Reset Due to SDA Arbitration During Start Condition240FIGURE 19-31: Bus Collision During a Repeated Start Condition (Case 1)241FIGURE 19-32: Bus Collision During Repeated Start Condition (Case 2)241FIGURE 19-33: Bus Collision During a Stop Condition (Case 1)242FIGURE 19-34: Bus Collision During a Stop Condition (Case 2)242TABLE 19-4: Registers Associated with I2C™ Operation24320.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)245Register 20-1: TXSTA: Transmit Status And Control Register246Register 20-2: RCSTA: Receive Status And Control Register247Register 20-3: BAUDCON: Baud Rate Control Register24820.1 Baud Rate Generator (BRG)24920.1.1 Operation in Power-Managed Modes24920.1.2 Sampling249TABLE 20-1: Baud Rate Formulas249EXAMPLE 20-1: Calculating Baud Rate Error250TABLE 20-2: Registers Associated with Baud Rate Generator250TABLE 20-3: Baud Rates for Asynchronous Modes25120.1.3 Auto-Baud Rate Detect253TABLE 20-4: BRG Counter Clock Rates253FIGURE 20-1: Automatic Baud Rate Calculation254FIGURE 20-2: BRG Overflow Sequence25420.2 EUSART Asynchronous Mode25520.2.1 EUSART Asynchronous Transmitter255FIGURE 20-3: EUSART Transmit Block Diagram256FIGURE 20-4: Asynchronous Transmission, TXCKP = 0 (TX Not Inverted)256FIGURE 20-5: Asynchronous Transmission (Back to Back), TXCKP = 0 (TX Not Inverted)256TABLE 20-5: Registers Associated with Asynchronous Transmission25720.2.2 EUSART Asynchronous Receiver25820.2.3 Setting Up 9-Bit Mode with Address Detect258FIGURE 20-6: EUSART Receive Block Diagram259FIGURE 20-7: Asynchronous Reception, RXDTP = 0 (RX Not Inverted)259TABLE 20-6: Registers Associated with Asynchronous Reception25920.2.4 Auto-Wake-up on Sync Break Character260FIGURE 20-8: Auto-Wake-up Bit (WUE) Timings During Normal Operation260FIGURE 20-9: Auto-Wake-up Bit (WUE) Timings During Sleep26020.2.5 Break Character Sequence26120.2.6 Receiving A Break Character261FIGURE 20-10: Send Break Character Sequence26120.3 EUSART Synchronous Master Mode26220.3.1 EUSART Synchronous Master Transmission262FIGURE 20-11: Synchronous Transmission262FIGURE 20-12: Synchronous Transmission (Through TXEN)263TABLE 20-7: Registers Associated with Synchronous Master Transmission26320.3.2 EUSART Synchronous Master Reception264FIGURE 20-13: Synchronous Reception (Master Mode, SREN)264TABLE 20-8: Registers Associated with Synchronous Master Reception26420.4 EUSART Synchronous Slave Mode26520.4.1 EUSART Synchronous Slave Transmission265TABLE 20-9: Registers Associated with Synchronous Slave Transmission26520.4.2 EUSART Synchronous Slave Reception266TABLE 20-10: Registers Associated with Synchronous Slave Reception26621.0 10-Bit Analog-to-Digital Converter (A/D) Module267Register 21-1: ADCON0: A/D Control Register 0267Register 21-2: ADCON1: A/D Control Register 1268Register 21-3: ADCON2: A/D Control Register 2269FIGURE 21-1: A/D Block Diagram270FIGURE 21-2: A/D Transfer Function271FIGURE 21-3: Analog Input Model27121.1 A/D Acquisition Requirements272EQUATION 21-1: Acquisition Time272EQUATION 21-2: A/D Minimum Charging Time272EQUATION 21-3: Calculating the Minimum Required Acquisition Time27221.2 Selecting and Configuring Acquisition Time27321.3 Selecting the A/D Conversion Clock273TABLE 21-1: Tad vs. Device Operating Frequencies27321.4 Operation in Power-Managed Modes27421.5 Configuring Analog Port Pins27421.6 A/D Conversions27521.7 Discharge275FIGURE 21-4: A/D Conversion Tad Cycles (ACQT<2:0> = 000, Tacq = 0)275FIGURE 21-5: A/D Conversion Tad Cycles (ACQT<2:0> = 010, Tacq = 4 Tad)27521.8 Use of the CCP2 Trigger276TABLE 21-2: Registers Associated with A/D Operation27622.0 Comparator Module277Register 22-1: CMCON: Comparator Control Register27722.1 Comparator Configuration278FIGURE 22-1: Comparator I/O Operating Modes27822.2 Comparator Operation27922.3 Comparator Reference279FIGURE 22-2: Single Comparator27922.3.1 External Reference Signal27922.3.2 Internal Reference Signal27922.4 Comparator Response Time27922.5 Comparator Outputs279FIGURE 22-3: Comparator Output Block Diagram28022.6 Comparator Interrupts28022.7 Comparator Operation During Sleep28022.8 Effects of a Reset28022.9 Analog Input Connection Considerations281FIGURE 22-4: Comparator Analog Input Model281TABLE 22-1: Registers Associated with Comparator Module28123.0 Comparator Voltage Reference Module28323.1 Configuring the Comparator Voltage Reference283Register 23-1: CVRCON: Comparator Voltage Reference Control Register283FIGURE 23-1: Comparator Voltage Reference Block Diagram28423.2 Voltage Reference Accuracy/Error28423.3 Operation During Sleep28423.4 Effects of a Reset28423.5 Connection Considerations284FIGURE 23-2: Comparator Voltage Reference Output Buffer Example285TABLE 23-1: Registers Associated with Comparator Voltage Reference28524.0 High/Low-Voltage Detect (HLVD)287Register 24-1: HLVDCON: High/Low-Voltage Detect Control Register28724.1 Operation288FIGURE 24-1: HLVD Module Block Diagram (with External Input)28824.2 HLVD Setup28924.3 Current Consumption28924.4 HLVD Start-up Time289FIGURE 24-2: Low-Voltage Detect Operation (VDIRMAG = 0)289FIGURE 24-3: High-Voltage Detect Operation (VDIRMAG = 1)29024.5 Applications290FIGURE 24-4: Typical High/Low-Voltage Detect Application29024.6 Operation During Sleep29124.7 Effects of a Reset291TABLE 24-1: Registers Associated with High/Low-Voltage Detect Module29125.0 Special Features of the CPU29325.1 Configuration Bits294TABLE 25-1: Configuration Bits and Device IDs294Register 25-1: CONFIG1L: CoNfiguration Register 1 Low (Byte Address 300000h)295Register 25-2: CONFIG1H: Configuration Register 1 High (Byte Address 300001h)296Register 25-3: CONFIG2L: Configuration Register 2 Low (Byte AdDREss 300002h)297Register 25-4: CONFIG2H: Configuration Register 2 High (Byte Address 300003h)298Register 25-5: CONFIG3H: Configuration Register 3 High (Byte Address 300005h)299Register 25-6: CONFIG4L: Configuration Register 4 Low (Byte Address 300006h)300Register 25-7: CONFIG5L: Configuration Register 5 Low (Byte Address 300008h)301Register 25-8: CONFIG5H: Configuration Register 5 High (Byte Address 300009h)301Register 25-9: CONFIG6L: Configuration Register 6 Low (Byte Address 30000Ah)302Register 25-10: CONFIG6H: Configuration Register 6 High (Byte Address 30000Bh)302Register 25-11: CONFIG7L: Configuration Register 7 Low (Byte Address 30000Ch)303Register 25-12: CONFIG7H: Configuration Register 7 High (Byte Address 30000Dh)303Register 25-13: DEVID1: Device ID Register 1 for PIC18F2455/2550/4455/4550 Devices304Register 25-14: DEVID2: Device ID Register 2 for PIC18F2455/2550/4455/4550 Devices30425.2 Watchdog Timer (WDT)30525.2.1 Control Register305FIGURE 25-1: WDT Block Diagram305Register 25-15: WDTCON: Watchdog Timer Control Register306TABLE 25-2: Summary of Watchdog Timer Registers30625.3 Two-Speed Start-up30725.3.1 Special Considerations for Using Two-Speed Start-up307FIGURE 25-2: Timing Transition for Two-Speed Start-up (INTOSC to HSPLL)30725.4 Fail-Safe Clock Monitor308FIGURE 25-3: FSCM Block Diagram30825.4.1 FSCM and the Watchdog Timer30825.4.2 Exiting Fail-Safe Operation308FIGURE 25-4: FSCM Timing Diagram30925.4.3 FSCM Interrupts in Power-Managed Modes30925.4.4 POR or Wake-up From Sleep30925.5 Program Verification and Code Protection310FIGURE 25-5: Code-Protected Program Memory310TABLE 25-3: Summary of Code Protection Registers31025.5.1 Program Memory Code Protection311FIGURE 25-6: Table Write (WRTx) Disallowed311FIGURE 25-7: External Block Table Read (EBTRx) Disallowed312FIGURE 25-8: External Block Table Read (EBTRx) Allowed31225.5.2 Data EEPROM Code Protection31325.5.3 Configuration Register Protection31325.6 ID Locations31325.7 In-Circuit Serial Programming31325.8 In-Circuit Debugger313TABLE 25-4: Debugger Resources31325.9 Special ICPORT Features (44-Pin TQFP Package Only)31325.9.1 Dedicated ICD/ICSP Port313TABLE 25-5: Equivalent Pins for Legacy and Dedicated ICD/ICSP™ Ports31325.9.2 28-Pin Emulation31425.10 Single-Supply ICSP Programming31426.0 Instruction Set Summary31526.1 Standard Instruction Set315TABLE 26-1: Opcode Field Descriptions316FIGURE 26-1: General Format for Instructions317TABLE 26-2: PIC18FXXXX Instruction Set31826.1.1 Standard Instruction Set32126.2 Extended Instruction Set35726.2.1 Extended Instruction Syntax357TABLE 26-3: Extensions to the PIC18 Instruction Set35726.2.2 Extended Instruction Set35826.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode36226.2.4 Considerations When Enabling the Extended Instruction Set36226.2.5 Special Considerations with Microchip MPLAB® IDE Tools36427.0 Development Support36527.1 MPLAB Integrated Development Environment Software36527.2 MPASM Assembler36627.3 MPLAB C18 and MPLAB C30 C Compilers36627.4 MPLINK Object Linker/ MPLIB Object Librarian36627.5 MPLAB ASM30 Assembler, Linker and Librarian36627.6 MPLAB SIM Software Simulator36627.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator36727.8 MPLAB REAL ICE In-Circuit Emulator System36727.9 MPLAB ICD 2 In-Circuit Debugger36727.10 MPLAB PM3 Device Programmer36727.11 PICSTART Plus Development Programmer36827.12 PICkit 2 Development Programmer36827.13 Demonstration, Development and Evaluation Boards36828.0 Electrical Characteristics369Absolute Maximum Ratings(†)369FIGURE 28-1: PIC18F2455/2550/4455/4550 Voltage-Frequency Graph (Industrial)370FIGURE 28-2: PIC18LF2455/2550/4455/4550 Voltage-Frequency Graph (Industrial Low Voltage)37028.1 DC Characteristics: Supply Voltage PIC18F2455/2550/4455/4550 (Industrial) PIC18LF2455/2550/4455/4550 (Industrial)37128.2 DC Characteristics: Power-Down and Supply Current PIC18F2455/2550/4455/4550 (Industrial) PIC18LF2455/2550/4455/4550 (Industrial)37228.3 DC Characteristics: PIC18F2455/2550/4455/4550 (Industrial) PIC18LF2455/2550/4455/4550 (Industrial)381TABLE 28-1: Memory Programming Requirements383TABLE 28-2: Comparator Specifications384TABLE 28-3: Voltage Reference Specifications384TABLE 28-4: USB Module Specifications385TABLE 28-5: USB Internal Voltage Regulator Specifications385FIGURE 28-3: High/Low-Voltage Detect Characteristics386TABLE 28-6: High/Low-Voltage Detect Characteristics38628.4 AC (Timing) Characteristics38728.4.1 Timing Parameter Symbology38728.4.2 Timing Conditions388TABLE 28-7: Temperature and Voltage Specifications – AC388FIGURE 28-4: Load Conditions for Device Timing Specifications38828.4.3 Timing Diagrams And Specifications389FIGURE 28-5: External Clock Timing (All Modes Except PLL)389TABLE 28-8: External Clock Timing Requirements389TABLE 28-9: PLL Clock Timing Specifications (Vdd = 3.0V to 5.5V)390TABLE 28-10: AC Characteristics: Internal RC Accuracy PIC18F2455/2550/4455/4550 (Industrial) PIC18LF2455/2550/4455/4550 (Industrial)390FIGURE 28-6: CLKO and I/O Timing391TABLE 28-11: CLKO and I/O Timing Requirements391FIGURE 28-7: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing392FIGURE 28-8: Brown-out Reset Timing392TABLE 28-12: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements392FIGURE 28-9: Timer0 and Timer1 External Clock Timings393TABLE 28-13: Timer0 and Timer1 External Clock Requirements393FIGURE 28-10: Capture/Compare/PWM Timings (All CCP Modules)394TABLE 28-14: Capture/Compare/PWM Requirements (All CCP Modules)394FIGURE 28-11: Example SPI Master Mode Timing (CKE = 0)395TABLE 28-15: Example SPI Mode Requirements (Master Mode, CKE = 0)395FIGURE 28-12: Example SPI Master Mode Timing (CKE = 1)396TABLE 28-16: Example SPI Mode Requirements (Master Mode, CKE = 1)396FIGURE 28-13: Example SPI Slave Mode Timing (CKE = 0)397TABLE 28-17: Example SPI Mode Requirements (Slave Mode Timing, CKE = 0)397FIGURE 28-14: Example SPI Slave Mode Timing (CKE = 1)398TABLE 28-18: Example SPI Slave Mode Requirements (CKE = 1)398FIGURE 28-15: I2C™ Bus Start/Stop Bits Timing399TABLE 28-19: I2C™ Bus Start/Stop Bits Requirements (Slave Mode)399FIGURE 28-16: I2C™ Bus Data Timing399TABLE 28-20: I2C™ Bus Data Requirements (Slave Mode)400FIGURE 28-17: Master SSP I2C™ Bus Start/Stop Bits Timing Waveforms401TABLE 28-21: Master SSP I2C™ Bus Start/Stop Bits Requirements401FIGURE 28-18: Master SSP I2C™ Bus Data Timing401TABLE 28-22: Master SSP I2C™ Bus Data Requirements402FIGURE 28-19: EUSART Synchronous Transmission (Master/Slave) Timing403TABLE 28-23: EUSART Synchronous Transmission Requirements403FIGURE 28-20: EUSART Synchronous Receive (Master/Slave) Timing403TABLE 28-24: EUSART Synchronous Receive Requirements403FIGURE 28-21: USB Signal Timing404TABLE 28-25: USB Low-Speed Timing Requirements404TABLE 28-26: USB Full-Speed Requirements404FIGURE 28-22: Streaming Parallel Port Timing (PIC18F4455/4550)405TABLE 28-27: Streaming Parallel Port Requirements (PIC18F4455/4550)405TABLE 28-28: A/D Converter Characteristics: PIC18F2455/2550/4455/4550 (Industrial) PIC18LF2455/2550/4455/4550 (Industrial)406FIGURE 28-23: A/D Conversion Timing406TABLE 28-29: A/D Conversion Requirements40729.0 DC and AC Characteristics Graphs and Tables40930.0 Packaging Information41130.1 Package Marking Information411Package Marking Information (Continued)41230.2 Package Details413Appendix A: Revision History421Revision A (May 2004)421Revision B (October 2004)421Revision C (February 2006)421Revision D (January 2007)421Revision E (August 2008)421Appendix B: Device Differences421TABLE B-1: Device Differences421Appendix C: Conversion Considerations422Appendix D: Migration From Baseline to Enhanced Devices422Appendix E: Migration From Mid-Range to Enhanced Devices423Appendix F: Migration From High-End to Enhanced Devices423INDEX425The Microchip Web Site435Customer Change Notification Service435Customer Support435Reader Response436PIC18F2455/2550/4455/4550 Product Identification System437Worldwide Sales and Service438Size: 6.82 MBPages: 438Language: EnglishOpen manual
