Microchip Technology GPIODM-KPLCD Data Sheet

© 2009 Microchip Technology Inc.

 

DS39632E-page 149

The CCPRxH register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
When the CCPRxH and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCPx pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:

  

   

15.4.3

PWM AUTO-SHUTDOWN 
(CCP1 ONLY)

The PWM auto-shutdown features of the Enhanced CCP
module are also available to CCP1 in 28-pin devices. The
operation of this feature is discussed in detail in
Section 16.4.7 “Enhanced PWM Auto-Shutdown”.
Auto-shutdown features are not available for CCP2.

15.4.4

SETUP FOR PWM OPERATION

The following steps should be taken when configuring
the CCPx module for PWM operation:
1.

Set the PWM period by writing to the PR2
register.

2.

Set the PWM duty cycle by writing to the
CCPRxL register and CCPxCON<5:4> bits.

3.

Make the CCPx pin an output by clearing the
appropriate TRIS bit.

4.

Set the TMR2 prescale value, then enable
Timer2 by writing to T2CON.

5.

Configure the CCPx module for PWM operation.

If the PWM duty cycle value is longer than
the PWM period, the CCPx pin will not be
cleared.

F

OSC

F

PWM

---------------

⎝

⎠

⎛

⎞

log

2

( )

log

-----------------------------bits

=

PWM Resolution (max)

Timer  Prescaler  (1,  4,  16)

16

4

1

1

1

1

PR2 Value

FFh

FFh

FFh

3Fh

1Fh

17h

Maximum Resolution (bits)

10

10

10

8

7

6.58