Microchip Technology GPIODM-KPLCD Data Sheet
© 2009 Microchip Technology Inc.
DS39632E-page 175
PIC18F2455/2550/4455/4550
The BDnSTAT byte of the BDT should always be the
last byte updated when preparing to arm an endpoint.
The SIE will clear the UOWN bit when a transaction
has completed. The only exception to this is when KEN
is enabled and/or BSTALL is enabled.
No hardware mechanism exists to block access when
the UOWN bit is set. Thus, unexpected behavior can
occur if the microcontroller attempts to modify memory
when the SIE owns it. Similarly, reading such memory
may produce inaccurate data until the USB peripheral
returns ownership to the microcontroller.
last byte updated when preparing to arm an endpoint.
The SIE will clear the UOWN bit when a transaction
has completed. The only exception to this is when KEN
is enabled and/or BSTALL is enabled.
No hardware mechanism exists to block access when
the UOWN bit is set. Thus, unexpected behavior can
occur if the microcontroller attempts to modify memory
when the SIE owns it. Similarly, reading such memory
may produce inaccurate data until the USB peripheral
returns ownership to the microcontroller.
17.4.1.2
BDnSTAT Register (CPU Mode)
When UOWN = 0, the microcontroller core owns the
BD. At this point, the other seven bits of the register
take on control functions.
The Keep Enable bit, KEN (BDnSTAT<5>), determines
if a BD stays enabled. If the bit is set, once the UOWN
bit is set, it will remain owned by the SIE independent
of the endpoint activity. This prevents the USTAT FIFO
from being updated, as well as the transaction
complete interrupt from being set for the endpoint. This
feature should only be enabled when the Streaming
Parallel Port is selected as the data I/O channel instead
of USB RAM.
The Address Increment Disable bit, INCDIS
(BDnSTAT<4>), controls the SIE’s automatic address
increment function. Setting INCDIS disables the
auto-increment of the buffer address by the SIE for
each byte transmitted or received. This feature should
only be enabled when using the Streaming Parallel
Port, where each data byte is processed to or from the
same memory location.
The Data Toggle Sync Enable bit, DTSEN
(BDnSTAT<3>), controls data toggle parity checking.
Setting DTSEN enables data toggle synchronization by
BD. At this point, the other seven bits of the register
take on control functions.
The Keep Enable bit, KEN (BDnSTAT<5>), determines
if a BD stays enabled. If the bit is set, once the UOWN
bit is set, it will remain owned by the SIE independent
of the endpoint activity. This prevents the USTAT FIFO
from being updated, as well as the transaction
complete interrupt from being set for the endpoint. This
feature should only be enabled when the Streaming
Parallel Port is selected as the data I/O channel instead
of USB RAM.
The Address Increment Disable bit, INCDIS
(BDnSTAT<4>), controls the SIE’s automatic address
increment function. Setting INCDIS disables the
auto-increment of the buffer address by the SIE for
each byte transmitted or received. This feature should
only be enabled when using the Streaming Parallel
Port, where each data byte is processed to or from the
same memory location.
The Data Toggle Sync Enable bit, DTSEN
(BDnSTAT<3>), controls data toggle parity checking.
Setting DTSEN enables data toggle synchronization by
the SIE. When enabled, it checks the data packet’s par-
ity against the value of DTS (BDnSTAT<6>). If a packet
arrives with an incorrect synchronization, the data will
essentially be ignored. It will not be written to the USB
RAM and the USB transfer complete interrupt flag will
not be set. The SIE will send an ACK token back to the
host to Acknowledge receipt, however. The effects of
the DTSEN bit on the SIE are summarized in
Table 17-3.
The Buffer Stall bit, BSTALL (BDnSTAT<2>), provides
support for control transfers, usually one-time stalls on
Endpoint 0. It also provides support for the
SET_FEATURE/CLEAR_FEATURE commands speci-
fied in Chapter 9 of the USB specification; typically,
continuous STALLs to any endpoint other than the
default control endpoint.
The BSTALL bit enables buffer stalls. Setting BSTALL
causes the SIE to return a STALL token to the host if a
received token would use the BD in that location. The
EPSTALL bit in the corresponding UEPn control regis-
ter is set and a STALL interrupt is generated when a
STALL is issued to the host. The UOWN bit remains set
and the BDs are not changed unless a SETUP token is
received. In this case, the STALL condition is cleared
and the ownership of the BD is returned to the
microcontroller core.
The BD9:BD8 bits (BDnSTAT<1:0>) store the two most
significant digits of the SIE byte count; the lower 8 digits
are stored in the corresponding BDnCNT register. See
Section 17.4.2 “BD Byte Count” for more
information.
ity against the value of DTS (BDnSTAT<6>). If a packet
arrives with an incorrect synchronization, the data will
essentially be ignored. It will not be written to the USB
RAM and the USB transfer complete interrupt flag will
not be set. The SIE will send an ACK token back to the
host to Acknowledge receipt, however. The effects of
the DTSEN bit on the SIE are summarized in
Table 17-3.
The Buffer Stall bit, BSTALL (BDnSTAT<2>), provides
support for control transfers, usually one-time stalls on
Endpoint 0. It also provides support for the
SET_FEATURE/CLEAR_FEATURE commands speci-
fied in Chapter 9 of the USB specification; typically,
continuous STALLs to any endpoint other than the
default control endpoint.
The BSTALL bit enables buffer stalls. Setting BSTALL
causes the SIE to return a STALL token to the host if a
received token would use the BD in that location. The
EPSTALL bit in the corresponding UEPn control regis-
ter is set and a STALL interrupt is generated when a
STALL is issued to the host. The UOWN bit remains set
and the BDs are not changed unless a SETUP token is
received. In this case, the STALL condition is cleared
and the ownership of the BD is returned to the
microcontroller core.
The BD9:BD8 bits (BDnSTAT<1:0>) store the two most
significant digits of the SIE byte count; the lower 8 digits
are stored in the corresponding BDnCNT register. See
Section 17.4.2 “BD Byte Count” for more
information.
TABLE 17-3:
EFFECT OF DTSEN BIT ON ODD/EVEN (DATA0/DATA1) PACKET RECEPTION
OUT Packet
from Host
BDnSTAT Settings
Device Response after Receiving Packet
DTSEN
DTS
Handshake UOWN
TRNIF
BDnSTAT and USTAT Status
DATA0
1
0
ACK
0
1
Updated
DATA1
1
0
ACK
1
0
Not Updated
DATA1
1
1
ACK
0
1
Updated
DATA0
1
1
ACK
1
0
Not Updated
Either
0
x
ACK
0
1
Updated
Either, with error
x
x
NAK
1
0
Not Updated
Legend: x = don’t care