Microchip Technology GPIODM-KPLCD Data Sheet
© 2009 Microchip Technology Inc.
DS39632E-page 201
PIC18F2455/2550/4455/4550
19.3.3
ENABLING SPI I/O
To enable the serial port, MSSP Enable bit, SSPEN
(SSPCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, reinitialize the SSPCON
registers and then set the SSPEN bit. This configures
the SDI, SDO, SCK and SS pins as serial port pins. For
the pins to behave as the serial port function, some must
have their data direction bits (in the TRIS register)
appropriately programmed as follows:
• SDI must have TRISB<0> bit set (configure as
(SSPCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, reinitialize the SSPCON
registers and then set the SSPEN bit. This configures
the SDI, SDO, SCK and SS pins as serial port pins. For
the pins to behave as the serial port function, some must
have their data direction bits (in the TRIS register)
appropriately programmed as follows:
• SDI must have TRISB<0> bit set (configure as
digital in ADCON1)
• SDO must have TRISC<7> bit cleared
• SCK (Master mode) must have TRISB<1> bit
• SCK (Master mode) must have TRISB<1> bit
cleared
• SCK (Slave mode) must have TRISB<1> bit set
(configure as digital in ADCON1)
• SS must have TRISA<5> bit set (configure as
digital in ADCON1)
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value. Input
functions which will not be used do not need to be
configured as digital inputs.
overridden by programming the corresponding data
direction (TRIS) register to the opposite value. Input
functions which will not be used do not need to be
configured as digital inputs.
19.3.4
TYPICAL CONNECTION
Figure 19-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their
programmed clock edge and latched on the opposite
edge of the clock. Both processors should be pro-
grammed to the same Clock Polarity (CKP), then both
controllers would send and receive data at the same
time. Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends data
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their
programmed clock edge and latched on the opposite
edge of the clock. Both processors should be pro-
grammed to the same Clock Polarity (CKP), then both
controllers would send and receive data at the same
time. Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends data
– Slave sends dummy data
• Master sends data
– Slave sends data
• Master sends dummy data
– Slave sends data
FIGURE 19-2:
SPI MASTER/SLAVE CONNECTION
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
MSb
LSb
SDO
SDI
PROCESSOR 1
SCK
SPI Master SSPM3:SSPM0 = 00xxb
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
LSb
MSb
SDI
SDO
PROCESSOR 2
SCK
SPI Slave SSPM3:SSPM0 = 010xb
Serial Clock