Microchip Technology GPIODM-KPLCD Data Sheet
PIC18F2455/2550/4455/4550
DS39632E-page 222
© 2009 Microchip Technology Inc.
19.4.4.5
Clock Synchronization and
the CKP bit
the CKP bit
When the CKP bit is cleared, the SCL output is forced
to ‘0’. However, clearing the CKP bit will not assert the
SCL output low until the SCL output is already
sampled low. Therefore, the CKP bit will not assert the
SCL line until an external I
to ‘0’. However, clearing the CKP bit will not assert the
SCL output low until the SCL output is already
sampled low. Therefore, the CKP bit will not assert the
SCL line until an external I
2
C master device has
already asserted the SCL line. The SCL output will
remain low until the CKP bit is set and all other
devices on the I
remain low until the CKP bit is set and all other
devices on the I
2
C bus have deasserted SCL. This
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCL (see
Figure 19-14).
minimum high time requirement for SCL (see
Figure 19-14).
FIGURE 19-14:
CLOCK SYNCHRONIZATION TIMING
SDA
SCL
DX – 1
DX
Write
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SSPCON1
CKP
Master device
deasserts clock
deasserts clock
Master device
asserts clock
asserts clock