Microchip Technology GPIODM-KPLCD Data Sheet
PIC18F2455/2550/4455/4550
DS39632E-page 256
© 2009 Microchip Technology Inc.
20.2.2
EUSART ASYNCHRONOUS
RECEIVER
RECEIVER
The receiver block diagram is shown in Figure 20-6.
The data is received on the RX pin and drives the data
recovery block. The data recovery block is actually a
high-speed shifter operating at x16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at F
The data is received on the RX pin and drives the data
recovery block. The data recovery block is actually a
high-speed shifter operating at x16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at F
OSC
. This mode would typically be used
in RS-232 systems.
The RXDTP bit (BAUDCON<5>) allows the RX signal to
be inverted (polarity reversed). Devices that buffer
signals from RS-232 to TTL levels also perform an inver-
sion of the signal (when RS-232 = positive, TTL = 0).
Inverting the polarity of the RX pin data by setting the
RXDTP bit allows for the use of circuits that provide
buffering without inverting the signal.
To set up an Asynchronous Reception:
1.
The RXDTP bit (BAUDCON<5>) allows the RX signal to
be inverted (polarity reversed). Devices that buffer
signals from RS-232 to TTL levels also perform an inver-
sion of the signal (when RS-232 = positive, TTL = 0).
Inverting the polarity of the RX pin data by setting the
RXDTP bit allows for the use of circuits that provide
buffering without inverting the signal.
To set up an Asynchronous Reception:
1.
Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
2.
Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
bit, SYNC, and setting bit, SPEN.
3.
If the signal at the RX pin is to be inverted, set
the RXDTP bit.
the RXDTP bit.
4.
If interrupts are desired, set enable bit, RCIE.
5.
If 9-bit reception is desired, set bit, RX9.
6.
Enable the reception by setting bit, CREN.
7.
Flag bit, RCIF, will be set when reception is
complete and an interrupt will be generated if
enable bit, RCIE, was set.
complete and an interrupt will be generated if
enable bit, RCIE, was set.
8.
Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
enabled) and determine if any error occurred
during reception.
9.
Read the 8-bit received data by reading the
RCREG register.
RCREG register.
10. If any error occurred, clear the error by clearing
enable bit, CREN.
11. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
set.
20.2.3
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
ADDRESS DETECT
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1.
To set up an Asynchronous Reception with Address
Detect Enable:
1.
Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
2.
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
the SYNC bit and setting the SPEN bit.
3.
If the signal at the RX pin is to be inverted, set
the RXDTP bit. If the signal from the TX pin is to
be inverted, set the TXCKP bit.
the RXDTP bit. If the signal from the TX pin is to
be inverted, set the TXCKP bit.
4.
If interrupts are required, set the RCEN bit and
select the desired priority level with the RCIP bit.
select the desired priority level with the RCIP bit.
5.
Set the RX9 bit to enable 9-bit reception.
6.
Set the ADDEN bit to enable address detect.
7.
Enable reception by setting the CREN bit.
8.
The RCIF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RCIE and GIE bits are set.
complete. The interrupt will be Acknowledged if
the RCIE and GIE bits are set.
9.
Read the RCSTA register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
error occurred during reception, as well as read
bit 9 of data (if applicable).
10. Read RCREG to determine if the device is being
addressed.
11. If any error occurred, clear the CREN bit.
12. If the device has been addressed, clear the
12. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
receive buffer and interrupt the CPU.