Microchip Technology GPIODM-KPLCD Data Sheet

© 2009 Microchip Technology Inc.

 

DS39632E-page 277

A single comparator is shown in Figure 22-2, along with
the relationship between the analog input levels and
the digital output. When the analog input at V

IN

+ is less

than the analog input V

IN

-, the output of the comparator

is a digital low level. When the analog input at V

IN

+ is

greater than the analog input V

IN

-, the output of the

comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 22-2 represent
the uncertainty, due to input offsets and response time.

Depending on the comparator operating mode, either
an external or internal voltage reference may be used.
The analog signal present at V

IN

- is compared to the

signal at V

IN

+ and the digital output of the comparator

is adjusted accordingly (Figure 22-2).

22.3.1

EXTERNAL REFERENCE SIGNAL

When external voltage references are used, the
comparator module can be configured to have the com-
parators operate from the same or different reference
sources. However, threshold detector applications may
require the same reference. The reference signal must
be between V

SS

 and V

DD

 and can be applied to either

pin of the comparator(s).

22.3.2

INTERNAL REFERENCE SIGNAL

The comparator module also allows the selection of an
internally generated voltage reference from the
comparator voltage reference module. This module is
described in more detail in Section 23.0 “Comparator
Voltage Reference Module”.
The internal reference is only available in the mode
where four inputs are multiplexed to two comparators
(CM2:CM0 = 110). In this mode, the internal voltage
reference is applied to the V

IN

+ pin of both

comparators. 

Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output has a valid level. If the internal ref-
erence is changed, the maximum delay of the internal
voltage reference must be considered when using the
comparator outputs. Otherwise, the maximum delay of
the comparators should be used (see Section 28.0
“Electrical Characteristics”).

The comparator outputs are read through the CMCON
register. These bits are read-only. The comparator
outputs may also be directly output to the RA4 and RA5
I/O pins. When enabled, multiplexors in the output path
of the RA4 and RA5 pins will switch and the output of
each pin will be the unsynchronized output of the
comparator. The uncertainty of each of the
comparators is related to the input offset voltage and
the response time given in the specifications.
Figure 22-3 shows the comparator output block
diagram.
The TRISA bits will still function as an output enable/
disable for the RA4 and RA5 pins while in this mode.
The polarity of the comparator outputs can be changed
using the C2INV and C1INV bits (CMCON<5:4>).         

–

+

V

IN

+

V

IN

-

Output

Output

V

IN

-

V

IN

+

Note 1: When reading the PORT register, all pins

configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.

2: Analog levels on any pin defined as a

digital input may cause the input buffer to
consume more current than is specified.