Microchip Technology GPIODM-KPLCD Data Sheet
PIC18F2455/2550/4455/4550
DS39632E-page 304
© 2009 Microchip Technology Inc.
TABLE 25-2:
SUMMARY OF WATCHDOG TIMER REGISTERS
REGISTER 25-15: WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
SWDTEN
(1)
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-1
Unimplemented: Read as ‘0’
bit 0
SWDTEN: Software Controlled Watchdog Timer Enable bit
(1)
1 = Watchdog Timer is on
0 = Watchdog Timer is off
0 = Watchdog Timer is off
Note 1:
This bit has no effect if the Configuration bit, WDTEN, is enabled.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
RCON
IPEN
SBOREN
(1)
—
RI
TO
PD
POR
BOR
WDTCON
—
—
—
—
—
—
—
SWDTEN
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
Note 1:
Note 1:
The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.