Microchip Technology GPIODM-KPLCD Data Sheet

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© 2009 Microchip Technology Inc.
 
DS39632E-page 33
PIC18F2455/2550/4455/4550
2.4.2
OSCILLATOR TRANSITIONS
PIC18F2455/2550/4455/4550 devices contain circuitry
to prevent clock “glitches” when switching between
clock sources. A short pause in the device clock occurs
during the clock switch. The length of this pause is the
sum of two cycles of the old clock source and three to
four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Clock transitions are discussed in greater detail in
Section 3.1.2 “Entering Power-Managed Modes”.
              
REGISTER 2-2:
OSCCON: OSCILLATOR CONTROL REGISTER 
R/W-0
R/W-1
R/W-0
R/W-0
R
(1)
R-0
R/W-0
R/W-0
IDLEN
IRCF2
IRCF1
IRCF0
OSTS
IOFS
SCS1
SCS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IDLEN: Idle Enable bit
1 = Device enters Idle mode on SLEEP instruction
0 = Device enters Sleep mode on SLEEP instruction
bit 6-4
IRCF2:IRCF0: Internal Oscillator Frequency Select bits
111 = 8 MHz (INTOSC drives clock directly)
110 = 4 MHz 
101 = 2 MHz 
100 = 1 MHz
(3)
 
011 = 500 kHz 
010 = 250 kHz
001 = 125 kHz
000 = 31 kHz (from either INTOSC/256 or INTRC directly)
(2)
bit 3
OSTS: Oscillator Start-up Time-out Status bit
(1)
1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running
0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready
bit 2
IOFS: INTOSC Frequency Stable bit 
1 = INTOSC frequency is stable
0 = INTOSC frequency is not stable
bit 1-0
SCS1:SCS0: System Clock Select bits
1x = Internal oscillator
01 = Timer1 oscillator
00 = Primary oscillator
Note 1:
Depends on the state of the IESO Configuration bit.
2:
Source selected by the INTSRC bit (OSCTUNE<7>), see text.
3:
Default output frequency of INTOSC on Reset.