Microchip Technology GPIODM-KPLCD Data Sheet
© 2009 Microchip Technology Inc.
DS39632E-page 387
PIC18F2455/2550/4455/4550
28.4.3
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 28-5:
EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
TABLE 28-8:
EXTERNAL CLOCK TIMING REQUIREMENTS
OSC1
CLKO
Q4
Q1
Q2
Q3
Q4
Q1
1
2
3
3
4
4
Param.
No.
Symbol
Characteristic
Min
Max
Units
Conditions
1A
F
OSC
External CLKI Frequency
(1)
Oscillator Frequency
(1)
DC
48
MHz
EC, ECIO Oscillator mode
0.2
1
MHz
XT, XTPLL Oscillator mode
4
25
(2)
MHz
HS Oscillator mode
4
24
(2)
MHz
HSPLL Oscillator mode
1
T
OSC
External CLKI Period
(1)
Oscillator Period
(1)
20.8
DC
ns
EC, ECIO Oscillator mode
1000
5000
ns
XT Oscillator mode
40
40
40
250
250
250
ns
ns
ns
HS Oscillator mode
HSPLL Oscillator mode
HSPLL Oscillator mode
2
T
CY
Instruction Cycle Time
(1)
83.3
DC
ns
T
CY
= 4/F
OSC
3
TosL,
TosH
TosH
External Clock in (OSC1)
High or Low Time
High or Low Time
30
—
ns
XT Oscillator mode
10
—
ns
HS Oscillator mode
4
TosR,
TosF
TosF
External Clock in (OSC1)
Rise or Fall Time
Rise or Fall Time
—
20
ns
XT Oscillator mode
—
7.5
ns
HS Oscillator mode
Note 1: Instruction cycle period (T
CY
) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
2:
When V
DD
>= 3.3V, the maximum crystal or resonator frequency is 25 MHz (or 24 MHz with PLL prescaler).
When 2.0V < V
DD
< 3.3V, the maximum crystal frequency = (16.36 MHz/V)(V
DD
– 2.0V) + 4 MHz.