Microchip Technology GPIODM-KPLCD Data Sheet
© 2009 Microchip Technology Inc.
DS39632E-page 403
PIC18F2455/2550/4455/4550
FIGURE 28-22:
STREAMING PARALLEL PORT TIMING (PIC18F4455/4550)
TABLE 28-27: STREAMING PARALLEL PORT REQUIREMENTS (PIC18F4455/4550)
OESPP
CSSPP
SPP<7:0>
Write Data
ToeF2adR
ToeF2adV
ToeR2adI
ToeF2daR
ToeF2daV
ToeR2adI
Note:
Refer to Figure 28-4 for load conditions.
Write Address
Param.
No.
Symbol
Characteristic
Min
Max
Units
Conditions
T07
ToeF2adR
OESPP Falling Edge to CSSPP Rising Edge,
Address Out
Address Out
0
5
ns
T08
ToeF2adV
OESPP Falling Edge to Address Out Valid
0
5
ns
T09
ToeR2adI
OESPP Rising Edge to Address Out Invalid
0
5
ns
T10
ToeF2daR
OESPP Falling Edge to CSSPP Rising Edge,
Data Out
Data Out
0
5
ns
T11
ToeF2daV
OESPP Falling Edge to Address Out Valid
0
5
ns
T12
ToeR2daI
OESPP Rising Edge to Data Out Invalid
0
5
ns