Microchip Technology GPIODM-KPLCD Data Sheet

DS39632E-page 39

PIC18F2455/2550/4455/4550

FIGURE 3-3:

TRANSITION TIMING TO RC_RUN MODE

FIGURE 3-4:

TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE

OSC1

Peripheral

Program

INTRC

Counter

Clock

CPU

Clock

PC + 2

n-1

Clock Transition

(1)

PC + 4

Note 1:

Clock transition typically occurs within 2-4 T

OSC

Q3 Q4

OSC1

Peripheral

Program

INTOSC

PLL Clock

PC + 4

Output

CPU Clock

PC + 2

Clock

Counter

Note 1:

OST

= 1024 T

OSC

; T

PLL

= 2 ms (approx). These intervals are not shown to scale.

Clock transition typically occurs within 2-4 T

OSC

SCS1:SCS0 bits Changed

PLL(1)

n-1 n

Clock

(2)

OSTS bit Set

Transition

Multiplexer

OST(1)