Microchip Technology GPIODM-KPLCD Data Sheet

DS39632E-page 52

 

© 2009 Microchip Technology Inc.

Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred. 
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCON register, RI, TO, PD,
POR and BOR, are set or cleared differently in different
Reset situations as indicated in Table 4-3. These bits
are used in software to determine the nature of the
Reset. 

Table 4-4 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.

Power-on Reset

0000h

1

1

1

0

0

0

0

RESET instruction

0000h

0

u

u

u

u

u

u

Brown-out Reset

0000h

1

1

1

u

0

u

u

MCLR Reset during power-managed Run 
modes

0000h

u

1

u

u

u

u

u

MCLR Reset during power-managed Idle 
modes and Sleep mode

0000h

u

1

0

u

u

u

u

WDT time-out during full power or 
power-managed Run modes

0000h

u

0

u

u

u

u

u

MCLR Reset during full-power execution

0000h

u

u

u

u

u

u

u

Stack Full Reset (STVREN = 1)

0000h

u

u

u

u

u

1

u

Stack Underflow Reset (STVREN = 1)

0000h

u

u

u

u

u

u

1

Stack Underflow Error (not an actual Reset, 
STVREN = 0)

0000h

u

u

u

u

u

u

1

WDT time-out during power-managed Idle or 
Sleep modes

PC + 2

u

0

0

u

u

u

u

Interrupt exit from power-managed modes

PC + 2

u

u

0

u

u

u

u

Legend: u = unchanged
Note 1:

When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the 
interrupt vector (008h or 0018h).

Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled 
(BOREN1:BOREN0 Configuration bits = 01 and SBOREN = 1); otherwise, the Reset state is ‘0’.