Microchip Technology GPIODM-KPLCD Data Sheet
© 2009 Microchip Technology Inc.
DS39632E-page 97
PIC18F2455/2550/4455/4550
8.0
8 x 8 HARDWARE MULTIPLIER
8.1
Introduction
All PIC18 devices include an 8 x 8 hardware multiplier
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the STATUS
register.
Making multiplication a hardware operation allows it to
be completed in a single instruction cycle. This has the
advantages of higher computational throughput and
reduced code size for multiplication algorithms and
allows the PIC18 devices to be used in many applica-
tions previously reserved for digital signal processors.
A comparison of various hardware and software
multiply operations, along with the savings in memory
and execution time, is shown in Table 8-1.
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the STATUS
register.
Making multiplication a hardware operation allows it to
be completed in a single instruction cycle. This has the
advantages of higher computational throughput and
reduced code size for multiplication algorithms and
allows the PIC18 devices to be used in many applica-
tions previously reserved for digital signal processors.
A comparison of various hardware and software
multiply operations, along with the savings in memory
and execution time, is shown in Table 8-1.
8.2
Operation
Example 8-1 shows the instruction sequence for an
8 x 8 unsigned multiplication. Only one instruction is
required when one of the arguments is already loaded
in the WREG register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiplication. To account for the sign bits of the
arguments, each argument’s Most Significant bit (MSb)
is tested and the appropriate subtractions are done.
8 x 8 unsigned multiplication. Only one instruction is
required when one of the arguments is already loaded
in the WREG register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiplication. To account for the sign bits of the
arguments, each argument’s Most Significant bit (MSb)
is tested and the appropriate subtractions are done.
EXAMPLE 8-1:
8 x 8 UNSIGNED
MULTIPLY ROUTINE
MULTIPLY ROUTINE
EXAMPLE 8-2:
8 x 8 SIGNED MULTIPLY
ROUTINE
ROUTINE
TABLE 8-1:
PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS
MOVF
ARG1, W
;
MULWF
ARG2
; ARG1 * ARG2 ->
; PRODH:PRODL
; PRODH:PRODL
MOVF
ARG1, W
MULWF
ARG2
; ARG1 * ARG2 ->
; PRODH:PRODL
; PRODH:PRODL
BTFSC
ARG2, SB
; Test Sign Bit
SUBWF
PRODH, F
; PRODH = PRODH
; - ARG1
; - ARG1
MOVF
ARG2, W
BTFSC
ARG1, SB
; Test Sign Bit
SUBWF
PRODH, F
; PRODH = PRODH
; - ARG2
; - ARG2
Routine
Multiply Method
Program
Memory
(Words)
Cycles
(Max)
Time
@ 40 MHz
@ 10 MHz
@ 4 MHz
8 x 8 unsigned
Without hardware multiply
13
69
6.9
μs
27.6
μs
69
μs
Hardware multiply
1
1
100 ns
400 ns
1
μs
8 x 8 signed
Without hardware multiply
33
91
9.1
μs
36.4
μs
91
μs
Hardware multiply
6
6
600 ns
2.4
μs
6
μs
16 x 16 unsigned
Without hardware multiply
21
242
24.2
μs
96.8
μs
242
μs
Hardware multiply
28
28
2.8
μs
11.2
μs
28
μs
16 x 16 signed
Without hardware multiply
52
254
25.4
μs
102.6
μs
254
μs
Hardware multiply
35
40
4.0
μs
16.0
μs
40
μs