Microchip Technology MA330026 Data Sheet
2011-2014 Microchip Technology Inc.
DS70000652F-page 37
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
3.0
CPU
The dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 CPU module has a
16-bit (data) modified Harvard architecture with an
enhanced instruction set, including significant support
for DSP. The CPU has a 24-bit instruction word with a
variable length opcode field. The Program Counter
(PC) is 23 bits wide and addresses up to 4M x 24 bits
of user program memory space. The actual amount of
program memory implemented varies by device. A
single-cycle instruction prefetch mechanism is used to
help maintain throughput and provides predictable
execution. All instructions execute in a single cycle,
with the exception of instructions that change the
program flow, the double-word move (MOV.D)
instruction and the table instructions. Overhead-free
program loop constructs are supported using the DO
and REPEAT instructions, both of which are
interruptible at any point.
dsPIC33FJ32(GP/MC)101/102/104 CPU module has a
16-bit (data) modified Harvard architecture with an
enhanced instruction set, including significant support
for DSP. The CPU has a 24-bit instruction word with a
variable length opcode field. The Program Counter
(PC) is 23 bits wide and addresses up to 4M x 24 bits
of user program memory space. The actual amount of
program memory implemented varies by device. A
single-cycle instruction prefetch mechanism is used to
help maintain throughput and provides predictable
execution. All instructions execute in a single cycle,
with the exception of instructions that change the
program flow, the double-word move (MOV.D)
instruction and the table instructions. Overhead-free
program loop constructs are supported using the DO
and REPEAT instructions, both of which are
interruptible at any point.
The dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 devices have six-
teen, 16-bit Working registers in the programmer’s
model. Each of the Working registers can serve as a
data, address, or address offset register. The 16th
Working register (W15) operates as a Software Stack
Pointer (SSP) for interrupts and calls.
dsPIC33FJ32(GP/MC)101/102/104 devices have six-
teen, 16-bit Working registers in the programmer’s
model. Each of the Working registers can serve as a
data, address, or address offset register. The 16th
Working register (W15) operates as a Software Stack
Pointer (SSP) for interrupts and calls.
There are two classes of instruction in the
dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/
MC)101/102/104 devices: MCU and DSP. These two
instruction classes are seamlessly integrated into a sin-
gle CPU. The instruction set includes many addressing
modes and is designed for optimum C compiler effi-
ciency. For most instructions, dsPIC33FJ16(GP/
MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104
devices are capable of executing a data (or program
data) memory read, a Working register (data) read, a
data memory write and a program (instruction) memory
read per instruction cycle. As a result, three parameter
instructions can be supported, allowing A + B = C
operations to be executed in a single cycle.
dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/
MC)101/102/104 devices: MCU and DSP. These two
instruction classes are seamlessly integrated into a sin-
gle CPU. The instruction set includes many addressing
modes and is designed for optimum C compiler effi-
ciency. For most instructions, dsPIC33FJ16(GP/
MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104
devices are capable of executing a data (or program
data) memory read, a Working register (data) read, a
data memory write and a program (instruction) memory
read per instruction cycle. As a result, three parameter
instructions can be supported, allowing A + B = C
operations to be executed in a single cycle.
, and
the programmer’s model for the dsPIC33FJ16(GP/
MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104
is shown in
MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104
is shown in
3.1
Data Addressing Overview
The data space can be addressed as 32K words or
64 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operates solely through the
X memory AGU, which accesses the entire memory
map as one linear data space. Certain DSP instructions
operate through the X and Y AGUs to support dual
operand reads, which splits the data address space
into two parts. The X and Y data space boundary is
device-specific.
64 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operates solely through the
X memory AGU, which accesses the entire memory
map as one linear data space. Certain DSP instructions
operate through the X and Y AGUs to support dual
operand reads, which splits the data address space
into two parts. The X and Y data space boundary is
device-specific.
Overhead-free circular buffers (Modulo Addressing
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the software
boundary checking overhead for DSP algorithms.
Furthermore, the X AGU circular addressing can be
used with any of the MCU class of instructions. The X
AGU also supports Bit-Reversed Addressing to greatly
simplify input or output data reordering for radix-2 FFT
algorithms.
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the software
boundary checking overhead for DSP algorithms.
Furthermore, the X AGU circular addressing can be
used with any of the MCU class of instructions. The X
AGU also supports Bit-Reversed Addressing to greatly
simplify input or output data reordering for radix-2 FFT
algorithms.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit
Program Space Visibility Page (PSVPAG) register. The
program-to-data-space mapping feature lets any
instruction access program space as if it were data
space.
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit
Program Space Visibility Page (PSVPAG) register. The
program-to-data-space mapping feature lets any
instruction access program space as if it were data
space.
3.2
DSP Engine Overview
The DSP engine features a high-speed, 17-bit by 17-bit
multiplier, a 40-bit ALU, two 40-bit saturating accumula-
tors and a 40-bit bidirectional barrel shifter. The barrel
shifter is capable of shifting a 40-bit value up to 16 bits
right or left, in a single cycle. The DSP instructions oper-
ate seamlessly with all other instructions and have been
designed for optimal real-time performance. The MAC
instruction and other associated instructions can concur-
rently fetch two data operands from memory, while
multiplying two W registers and accumulating and option-
ally saturating the result in the same cycle. This instruc-
tion functionality requires that the RAM data space be
split for these instructions and linear for all others. Data
space partitioning is achieved in a transparent and
flexible manner through dedicating certain Working
registers to each address space.
multiplier, a 40-bit ALU, two 40-bit saturating accumula-
tors and a 40-bit bidirectional barrel shifter. The barrel
shifter is capable of shifting a 40-bit value up to 16 bits
right or left, in a single cycle. The DSP instructions oper-
ate seamlessly with all other instructions and have been
designed for optimal real-time performance. The MAC
instruction and other associated instructions can concur-
rently fetch two data operands from memory, while
multiplying two W registers and accumulating and option-
ally saturating the result in the same cycle. This instruc-
tion functionality requires that the RAM data space be
split for these instructions and linear for all others. Data
space partitioning is achieved in a transparent and
flexible manner through dedicating certain Working
registers to each address space.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104
family devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “CPU” (DS70204) in the
“dsPIC33/PIC24 Family Reference Man-
ual”, which is available from the Microchip
web site (
and dsPIC33FJ32(GP/MC)101/102/104
family devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “CPU” (DS70204) in the
“dsPIC33/PIC24 Family Reference Man-
ual”, which is available from the Microchip
web site (
www.microchip.com
).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
available on all devices. Refer to
in
this data sheet for device-specific register
and bit information.
and bit information.