Microchip Technology MA330026 Data Sheet
2011-2014 Microchip Technology Inc.
DS70000652F-page 373
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
APPENDIX A:
REVISION HISTORY
Revision A (January 2011)
This is the initial released version of the document.
Revision B (February 2011)
.
In addition, minor text and formatting changes were
incorporated throughout the document.
incorporated throughout the document.
TABLE A-1:
MAJOR SECTION UPDATES
Section Name
Update Description
High-Performance, Ultra Low Cost 16-bit
Digital Signal Controllers
Digital Signal Controllers
Pin diagram updates (see “Pin Diagrams”):
• 20-pin PDIP/SOIC/SSOP (dsPIC33FJ16MC101):
Removed the FLTB1 pin from pin 10
• 28-pin SPDIP/SOIC/SSOP (dsPIC33FJ16MC102):
Relocated the FLTB1 pin from pin 12 to pin 14;
relocated the FLTA1 pin from pin 16 to pin 15
relocated the FLTA1 pin from pin 16 to pin 15
• 28-pin QFN (dsPIC33FJ16MC102):
Relocated the FLTA1 pin from pin 13 to pin 12;
relocated the FLTB1 pin from pin 9 to pin 11
relocated the FLTB1 pin from pin 9 to pin 11
• 36-pin TLA (dsPIC33FJ16MC102):
Relocated the FLTA1 pin from pin 17 to pin 16;
relocated the FLTB1 pin from pin 10 to pin 15
relocated the FLTB1 pin from pin 10 to pin 15
Section 1.0 “Device Overview”
Added Notes 1, 2, and 3 regarding the FLTA1 and FLTB1 pins to the
Pinout I/O Descriptions (see Table 1-1).
Pinout I/O Descriptions (see Table 1-1).
Added Section “”.
Section 4.0 “Memory Organization”
Updated All Resets value for PxFLTACON and PxFLTABCON to the
6-Output PWM1 Register Map (see Table 4-9).
6-Output PWM1 Register Map (see Table 4-9).
Added Note 1 to the PMD Register Map (see Table 4-29).
Section 6.0 “Resets”
Removed Reset timing sequence information from Section 6.2
“System Reset”, as this information is provided in Figure 6-2.
“System Reset”, as this information is provided in Figure 6-2.
Section 15.0 “Motor Control PWM Module” Added Note 2 and Note 3 regarding the FLTA1 and FLTB1 pins to the
6-channel PWM Module Block Diagram (see Figure 15-1).
Added Section 15.2 “PWM Faults” and Section 15.3 “Write-
protected Registers”.
protected Registers”.
Added Note 2 and Note 3 regarding the FLTA1 and FLTB1 pins to the
note boxes located below the PxFLTACON and PxFLTBCON
registers (see Register 15-9 and Register 15-10).
note boxes located below the PxFLTACON and PxFLTBCON
registers (see Register 15-9 and Register 15-10).
Section 17.0 “Inter-Integrated Circuit™
(I
(I
2
C™)”
Updated the descriptions for the conditional If STREN = 1 and If
STREN = 0 statements for the SCLREL bit in the I2Cx Control
Register (see Register 17-1).
STREN = 0 statements for the SCLREL bit in the I2Cx Control
Register (see Register 17-1).
Section 23.0 “Special Features”
Added the RTSP Effect column to the dsPIC33F Configuration Bits
Description (see Table 23-3).
Description (see Table 23-3).
Section 26.0 “Electrical Characteristics”
Added Parameters 300 and D305 (see Table 26-42 and Table 26-43).
Section 27.0 “Packaging Information”
Modified the pending TLA packaging page.