Microchip Technology AC164139 Data Sheet
2010 Microchip Technology Inc.
DS39969B-page 143
PIC24FJ256DA210 FAMILY
8.3
Control Registers
The following five Special Function Registers control
the operation of the oscillator:
• OSCCON
• CLKDIV
• OSCTUN
• CLKDIV2
• REFOCON
the operation of the oscillator:
• OSCCON
• CLKDIV
• OSCTUN
• CLKDIV2
• REFOCON
The OSCCON register (Register 8-1) is the main con-
trol register for the oscillator. It controls clock source
switching and allows the monitoring of clock sources.
The CLKDIV register (Register 8-2) controls the
features associated with Doze mode, as well as the
postscaler for the FRC oscillator.
The OSCTUN register (Register 8-3) allows the user to
fine tune the FRC oscillator over a range of
approximately ±1.5%.
The CLKDIV2 register (Register 8-4) controls the clock
to the display glass, with the frequency ranging from
750 kHz to 96 MHz.
The REFOCON register (Register 8-5) controls the
frequency of the reference clock out.
trol register for the oscillator. It controls clock source
switching and allows the monitoring of clock sources.
The CLKDIV register (Register 8-2) controls the
features associated with Doze mode, as well as the
postscaler for the FRC oscillator.
The OSCTUN register (Register 8-3) allows the user to
fine tune the FRC oscillator over a range of
approximately ±1.5%.
The CLKDIV2 register (Register 8-4) controls the clock
to the display glass, with the frequency ranging from
750 kHz to 96 MHz.
The REFOCON register (Register 8-5) controls the
frequency of the reference clock out.
REGISTER 8-1:
OSCCON: OSCILLATOR CONTROL REGISTER
U-0
R-x, HSC
(1)
R-x, HSC
(1)
R-x, HSC
(1)
U-0
R/W-x
(1)
R/W-x
(1)
R/W-x
(1)
—
COSC2
COSC1
COSC0
—
NOSC2
NOSC1
NOSC0
bit 15
bit 8
R/S-0
R/W-0
R-0, HSC
(3)
U-0
R/C-0, HS
R/W-0
R/W-0
R/W-0
CLKLOCK
IOLOCK
(2)
LOCK
—
CF
POSCEN
SOSCEN
OSWEN
bit 7
bit 0
Legend:
C = Clearable bit
S = Settable bit
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
HS = Hardware Settable bit
bit 15
Unimplemented: Read as ‘0’
bit 14-12
COSC<2:0>: Current Oscillator Selection bits
(1)
111
= Fast RC Oscillator with Postscaler (FRCDIV)
110
= Fast RC/16 Oscillator
101
= Low-Power RC Oscillator (LPRC)
100
= Secondary Oscillator (SOSC)
011
= Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)
010
= Primary Oscillator (XT, HS, EC)
001
= Fast RC Oscillator with Postscaler and PLL module (FRCPLL)
000
= Fast RC Oscillator (FRC)
bit 11
Unimplemented: Read as ‘0’
Note 1:
Reset values for these bits are determined by the FNOSC Configuration bits.
2:
The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In
addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared.
addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared.
3:
Also resets to ‘0’ during any valid clock switch or whenever a non PLL Clock mode is selected.