Microchip Technology AC164139 User Manuals

Table of Contents

• Graphics Controller Features:

  3
• Universal Serial Bus Features:

  3
• Peripheral Features:

  3
• High-Performance CPU

  4
• Power Management:

  4
• Analog Features:

  4
• Special Microcontroller Features:

  4
• Pin Diagram (64-Pin TQFP/QFN)

  5
• Pin Diagram (100-Pin TQFP)

  7
• Pin Diagram – Top View (121-Pin BGA)

  10
• Table of Contents

  13
• Most Current Data Sheet

  14
• Errata

  14
• Customer Notification System

  14
• 1.0 Device Overview

  15
  • 1.1 Core Features

    15
    • 1.1.1 16-Bit Architecture

      15
    • 1.1.2 Power-Saving Technology

      15
    • 1.1.3 Oscillator Options and Features

      15
    • 1.1.4 Easy Migration

      15
  • 1.2 Graphics Controller

    16
  • 1.3 USB On-The-Go

    16
  • 1.4 Other Special Features

    16
  • 1.5 Details on Individual Family Members

    17
    • TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ256DA210 family: 64-PIN

      18
    • TABLE 1-2: Device Features for the PIC24FJ256DA210 family: 100-pin Devices

      19
    • FIGURE 1-1: PIC24FJ256DA210 family General Block Diagram

      20
    • TABLE 1-3: PIC24FJ256DA210 family Pinout Descriptions

      21
• 2.0 Guidelines for Getting Started with 16-bit Microcontrollers

  33
  • 2.1 Basic Connection Requirements

    33
    • FIGURE 2-1: Recommended Minimum connections

      33
  • 2.2 Power Supply Pins

    34
    • 2.2.1 Decoupling Capacitors

      34
    • 2.2.2 Tank Capacitors

      34
  • 2.3 Master Clear (MCLR) Pin

    34
    • FIGURE 2-2: Example of MCLR Pin Connections

      34
  • 2.4 Voltage Regulator Pins (ENVREG/DISVREG and Vcap/Vddcore)

    35
    • FIGURE 2-3: Frequency vs. ESR Performance for Suggested Vcap

      35
  • 2.5 ICSP Pins

    35
  • 2.6 External Oscillator Pins

    36
    • FIGURE 2-4: Suggested Placement of the Oscillator Circuit

      36
  • 2.7 Configuration of Analog and Digital Pins During ICSP Operations

    37
  • 2.8 Unused I/Os

    37
• 3.0 CPU

  39
  • 3.1 Programmer’s Model

    39
    • FIGURE 3-1: PIC24F CPU Core Block Diagram

      40
    • TABLE 3-1: CPU Core Registers

      40
    • FIGURE 3-2: Programmer’s Model

      41
  • 3.2 CPU Control Registers

    42
    • Register 3-1: SR: ALU STATUS Register

      42
    • Register 3-2: CORCON: CPU Control Register

      43
  • 3.3 Arithmetic Logic Unit (ALU)

    43
    • 3.3.1 Multiplier

      43
    • 3.3.2 Divider

      44
    • 3.3.3 Multi-Bit Shift Support

      44
      • TABLE 3-2: Instructions that Use the Single Bit and Multi-Bit Shift Operation

        44
• 4.0 Memory Organization

  45
  • 4.1 Program Memory Space

    45
    • FIGURE 4-1: Program Space Memory Map for PIC24FJ256DA210 family Devices

      45
    • 4.1.1 Program Memory Organization

      46
    • 4.1.2 Hard Memory Vectors

      46
    • 4.1.3 Flash Configuration Words

      46
      • TABLE 4-1: Flash Configuration Words for PIC24FJ256DA210 family Devices

        46
      • FIGURE 4-2: Program Memory Organization

        46
  • 4.2 Data Memory Space

    47
    • TABLE 4-2: Total Memory Accessible by the Device

      47
    • 4.2.1 Data Space Width

      48
      • FIGURE 4-3: Data Space Memory Map for PIC24FJ256DA210 family Devices(4)

        48
    • 4.2.2 Data Memory Organization and Alignment

      49
    • 4.2.3 Near Data Space

      49
    • 4.2.4 Special Function Register (SFR) Space

      49
      • TABLE 4-3: Implemented Regions of SFR Data Space

        49
      • TABLE 4-4: CPU CORE Registers Map

        50
      • TABLE 4-5: ICN Register Map

        51
      • TABLE 4-6: Interrupt Controller Register Map

        52
      • TABLE 4-7: Timer Register Map

        53
      • TABLE 4-8: Input Capture Register Map

        54
      • TABLE 4-9: Output Compare Register Map

        55
      • TABLE 4-10: I2C™ Register Map

        56
      • TABLE 4-11: UART Register Maps

        57
      • TABLE 4-12: SPI Register Maps

        58
      • TABLE 4-13: PORTA Register Map(1)

        58
      • TABLE 4-14: PORTb Register Map

        58
      • TABLE 4-15: PORTC Register Map

        59
      • TABLE 4-16: PORTD Register Map

        59
      • TABLE 4-17: PORTE Register Map

        59
      • TABLE 4-18: PORTF Register Map

        60
      • TABLE 4-19: PORTG Register Map

        60
      • TABLE 4-20: Pad Configuration Register Map

        60
      • TABLE 4-21: ADC Register Map

        61
      • TABLE 4-22: CTMU Register Map

        62
      • TABLE 4-23: USB OTG Register Map

        63
      • TABLE 4-24: ANCFG Register Map

        64
      • TABLE 4-25: ANSEL Register Map

        64
      • TABLE 4-26: Enhanced Parallel Master/Slave Port Register Map(1)

        65
      • TABLE 4-27: Real-Time Clock and Calendar Register Map

        65
      • TABLE 4-28: Comparators Register Map

        66
      • TABLE 4-29: CRC Register Map

        66
      • TABLE 4-30: Peripheral Pin Select Register Map

        67
      • TABLE 4-31: Graphics Register Map

        69
      • TABLE 4-32: System Register Map

        70
      • TABLE 4-33: NVM Register Map

        70
      • TABLE 4-34: PMD Register Map

        70
    • 4.2.5 Extended Data Space (EDS)

      71
      • FIGURE 4-4: Extended Data Space

        71
      • FIGURE 4-5: EDS Address Generation for Read Operations

        72
      • EXAMPLE 4-1: EDS Read Code In Assembly

        72
      • FIGURE 4-6: EDS Address Generation for Write Operations

        73
      • EXAMPLE 4-2: EDS Write Code In Assembly

        73
      • TABLE 4-35: EDS Memory Address with Different Pages and Addresses

        74
    • 4.2.6 Software Stack

      75
      • FIGURE 4-7: CALL Stack Frame

        75
  • 4.3 Interfacing Program and Data Memory Spaces

    75
    • 4.3.1 Addressing Program Space

      75
      • TABLE 4-36: Program Space Address Construction

        76
      • FIGURE 4-8: Data Access from Program Space Address Generation

        76
    • 4.3.2 Data Access from Program Memory Using Table Instructions

      77
      • FIGURE 4-9: Accessing Program Memory with Table Instructions

        77
    • 4.3.3 Reading Data from Program Memory Using EDS

      78
      • TABLE 4-37: EDS Program Address with different Pages and Addresses

        78
      • FIGURE 4-10: Program Space Visibility Operation to Access Lower Word

        79
      • FIGURE 4-11: Program Space Visibility Operation to Access Higher Word

        79
      • EXAMPLE 4-3: EDS Read Code from Program Memory In Assembly

        80
• 5.0 Flash Program Memory

  81
  • 5.1 Table Instructions and Flash Programming

    81
    • FIGURE 5-1: Addressing for Table Registers

      81
  • 5.2 RTSP Operation

    82
  • 5.3 JTAG Operation

    82
  • 5.4 Enhanced In-Circuit Serial Programming

    82
  • 5.5 Control Registers

    82
  • 5.6 Programming Operations

    82
    • Register 5-1: NVMCON: Flash Memory Control Register

      83
    • 5.6.1 Programming Algorithm for Flash Program Memory

      84
      • EXAMPLE 5-1: Erasing a Program Memory Block (Assembly Language Code)

        84
      • EXAMPLE 5-2: Erasing a Program Memory Block (‘C’ Language Code)

        85
      • EXAMPLE 5-3: LOADING THE WRITE BUFFERS

        85
      • EXAMPLE 5-4: Initiating a Programming Sequence

        85
    • 5.6.2 Programming a single word of flash program memory

      86
      • EXAMPLE 5-5: Programming a Single Word of Flash Program Memory

        86
      • EXAMPLE 5-6: Programming a Single Word of Flash Program Memory (‘C’ Language Code)

        86
• 6.0 Resets

  87
  • FIGURE 6-1: Reset System Block Diagram

    87
  • Register 6-1: RCON: Reset Control Register(1)

    88
  • TABLE 6-1: Reset Flag Bit Operation

    89
  • 6.1 Special Function Register Reset States

    90
  • 6.2 Device Reset Times

    90
  • 6.3 Clock Source Selection at Reset

    90
    • TABLE 6-2: Oscillator Selection vs. Type of Reset (Clock Switching Enabled)

      90
    • TABLE 6-3: Reset Delay Times for Various Device Resets

      91
    • 6.3.1 POR and Long Oscillator Start-up Times

      91
    • 6.3.2 Fail-Safe Clock Monitor (FSCM) and Device Resets

      91
• 7.0 Interrupt Controller

  93
  • 7.1 Interrupt Vector Table

    93
    • 7.1.1 Alternate Interrupt Vector Table

      93
  • 7.2 Reset Sequence

    93
    • FIGURE 7-1: PIC24F Interrupt Vector Table

      94
    • TABLE 7-1: Trap Vector Details

      94
    • TABLE 7-2: Implemented Interrupt Vectors

      95
  • 7.3 Interrupt Control and Status Registers

    96
    • Register 7-1: SR: ALU STATUS Register (in CPU)

      97
    • Register 7-2: CORCON: CPU Control Register

      98
    • Register 7-3: INTCON1: Interrupt Control Register 1

      99
    • Register 7-4: INTCON2: Interrupt Control Register 2

      100
    • Register 7-5: IFS0: Interrupt Flag Status Register 0

      101
    • Register 7-6: IFS1: Interrupt Flag Status Register 1

      102
    • Register 7-7: IFS2: Interrupt Flag Status Register 2

      103
    • Register 7-8: IFS3: Interrupt Flag Status Register 3

      105
    • Register 7-9: IFS4: Interrupt Flag Status Register 4

      106
    • Register 7-10: IFS5: Interrupt Flag Status Register 5

      107
    • Register 7-11: IFS6: Interrupt Flag Status Register 6

      108
    • Register 7-12: IEC0: Interrupt Enable Control Register 0

      109
    • Register 7-13: IEC1: Interrupt Enable Control Register 1

      110
    • Register 7-14: IEC2: Interrupt Enable Control Register 2

      112
    • Register 7-15: IEC3: Interrupt Enable Control Register 3

      113
    • Register 7-16: IEC4: Interrupt Enable Control Register 4

      114
    • Register 7-17: IEC5: Interrupt Enable Control Register 5

      115
    • Register 7-18: IEC6: Interrupt Enable Control Register 6

      116
    • Register 7-19: IPC0: Interrupt Priority Control Register 0

      117
    • Register 7-20: IPC1: Interrupt Priority Control Register 1

      118
    • Register 7-21: IPC2: Interrupt Priority Control Register 2

      119
    • Register 7-22: IPC3: Interrupt Priority Control Register 3

      120
    • Register 7-23: IPC4: Interrupt Priority Control Register 4

      121
    • Register 7-24: IPC5: Interrupt Priority Control Register 5

      122
    • Register 7-25: IPC6: Interrupt Priority Control Register 6

      123
    • Register 7-26: IPC7: Interrupt Priority Control Register 7

      124
    • Register 7-27: IPC8: Interrupt Priority Control Register 8

      125
    • Register 7-28: IPC9: Interrupt Priority Control Register 9

      126
    • Register 7-29: IPC10: Interrupt Priority Control Register 10

      127
    • Register 7-30: IPC11: Interrupt Priority Control Register 11

      128
    • Register 7-31: IPC12: Interrupt Priority Control Register 12

      129
    • Register 7-32: IPC13: Interrupt Priority Control Register 13

      130
    • Register 7-33: IPC15: Interrupt Priority Control Register 15

      131
    • Register 7-34: IPC16: Interrupt Priority Control Register 16

      132
    • Register 7-35: IPC18: Interrupt Priority Control Register 18

      133
    • Register 7-36: IPC19: Interrupt Priority Control Register 19

      133
    • Register 7-37: IPC20: Interrupt Priority Control Register 20

      134
    • Register 7-38: IPC21: Interrupt Priority Control Register 21

      135
    • Register 7-39: IPC22: Interrupt Priority Control Register 22

      136
    • Register 7-40: IPC23: Interrupt Priority Control Register 23

      137
    • Register 7-41: IPC25: Interrupt Priority Control Register 25

      138
    • Register 7-42: INTTREG: Interrupt Controller Test Register

      139
  • 7.4 Interrupt Setup Procedures

    140
    • 7.4.1 Initialization

      140
    • 7.4.2 Interrupt Service Routine (ISR)

      140
    • 7.4.3 Trap Service Routine (TSR)

      140
    • 7.4.4 Interrupt Disable

      140
• 8.0 Oscillator Configuration

  141
  • FIGURE 8-1: PIC24FJ256DA210 family Clock Diagram

    141
  • 8.1 CPU Clocking Scheme

    142
  • 8.2 Initial Configuration on POR

    142
    • 8.2.1 Clock Switching Mode Configuration Bits

      142
      • TABLE 8-1: Configuration Bit Values for Clock Selection

        142
  • 8.3 Control Registers

    143
    • Register 8-1: OSCCON: Oscillator Control Register

      143
    • Register 8-2: CLKDIV: Clock Divider Register

      145
    • Register 8-3: OSCTUN: FRC Oscillator Tune Register

      146
    • Register 8-4: CLKDIV2: Clock Divider Register 2

      147
  • 8.4 Clock Switching Operation

    148
    • 8.4.1 Enabling Clock Switching

      148
    • 8.4.2 Oscillator Switching Sequence

      148
      • EXAMPLE 8-1: Basic Code Sequence for Clock Switching in Assembly

        149
  • 8.5 96 MHz PLL Block

    149
    • FIGURE 8-2: 96 MHz PLL Block

      150
    • 8.5.1 System Clock Generation

      150
      • TABLE 8-2: System Clock Options for 96 MHz PLL Block

        150
    • 8.5.2 USB Clock Generation

      151
      • TABLE 8-3: Valid Oscillator Configurations for USB Operations

        151
    • 8.5.3 Considerations for USB Operation

      151
    • 8.5.4 Graphics Clock Generation

      151
      • TABLE 8-4: Display Module Clock Frequency Division

        152
  • 8.6 Reference Clock Output

    152
    • Register 8-5: REFOCON: Reference Oscillator Control Register

      153
• 9.0 Power-Saving Features

  155
  • 9.1 Clock Frequency and Clock Switching

    155
  • 9.2 Instruction-Based Power-Saving Modes

    155
    • 9.2.1 Sleep Mode

      155
      • EXAMPLE 9-1: PWRSAV Instruction Syntax

        155
    • 9.2.2 Idle Mode

      156
    • 9.2.3 Interrupts Coincident with Power Save Instructions

      156
  • 9.3 Doze Mode

    156
  • 9.4 Selective Peripheral Module Control

    156
• 10.0 I/O Ports

  157
  • 10.1 Parallel I/O (PIO) Ports

    157
    • FIGURE 10-1: Block Diagram of a Typical Shared Port Structure

      157
    • 10.1.1 I/O Port Write/Read Timing

      158
    • 10.1.2 Open-Drain Configuration

      158
    • 10.1.3 Configuring D+ and D- Pins (RG2 and RG3)

      158
  • 10.2 Configuring Analog Port Pins (ANSEL)

    158
    • 10.2.1 Analog Input Pins and Voltage Considerations

      158
      • TABLE 10-1: Configuring Analog/Digital Function of an I/O Pin

        158
      • TABLE 10-2: Input Voltage Levels for Port or Pin Tolerated Description Input

        158
      • Register 10-1: ANSA: PortA Analog Function Selection Register(1)

        159
      • Register 10-2: ANSB: PortB Analog Function Selection Register

        160
      • Register 10-3: ANSC: PortC Analog Function Selection Register

        160
      • Register 10-4: ANSD: PortD Analog Function Selection Register

        161
      • Register 10-5: ANSE: PortE Analog Function Selection Register(1)

        161
      • Register 10-6: ANSF: PortF Analog Function Selection Register

        162
      • Register 10-7: ANSG: PortG Analog Function Selection Register

        162
  • 10.3 Input Change Notification

    163
    • EXAMPLE 10-1: Port Write/Read in Assembly

      163
    • EXAMPLE 10-2: Port Write/Read in ‘C’

      163
  • 10.4 Peripheral Pin Select (PPS)

    164
    • 10.4.1 Available Pins

      164
    • 10.4.2 Available Peripherals

      164
    • 10.4.3 Controlling Peripheral Pin Select

      164
      • TABLE 10-3: Selectable Input Sources (Maps Input to Function)(1)

        165
      • TABLE 10-4: Selectable Output Sources (Maps Function to Output)

        166
    • 10.4.4 Controlling Configuration Changes

      167
      • TABLE 10-5: Remappable Pin Exceptions for PIC24FJ256DA210 family Devices

        167
    • 10.4.5 Considerations for Peripheral Pin Selection

      168
      • EXAMPLE 10-3: Configuring UART1 Input and Output Functions

        168
    • 10.4.6 Peripheral Pin Select Registers

      169
      • Register 10-8: RPINR0: Peripheral Pin Select Input Register 0

        169
      • Register 10-9: RPINR1: Peripheral Pin Select Input Register 1

        169
      • Register 10-10: RPINR2: Peripheral Pin Select Input Register 2

        170
      • Register 10-11: RPINR3: Peripheral Pin Select Input Register 3

        170
      • Register 10-12: RPINR4: Peripheral Pin Select Input Register 4

        171
      • Register 10-13: RPINR7: Peripheral Pin Select Input Register 7

        171
      • Register 10-14: RPINR8: Peripheral Pin Select Input Register 8

        172
      • Register 10-15: RPINR9: Peripheral Pin Select Input Register 9

        172
      • Register 10-16: RPINR10: Peripheral Pin Select Input Register 10

        173
      • Register 10-17: RPINR11: Peripheral Pin Select Input Register 11

        173
      • Register 10-18: RPINR15: Peripheral Pin Select Input Register 15

        174
      • Register 10-19: RPINR17: Peripheral Pin Select Input Register 17

        174
      • Register 10-20: RPINR18: Peripheral Pin Select Input Register 18

        175
      • Register 10-21: RPINR19: Peripheral Pin Select Input Register 19

        175
      • Register 10-22: RPINR20: Peripheral Pin Select Input Register 20

        176
      • Register 10-23: RPINR21: Peripheral Pin Select Input Register 21

        176
      • Register 10-24: RPINR22: Peripheral Pin Select Input Register 22

        177
      • Register 10-25: RPINR23: Peripheral Pin Select Input Register 23

        177
      • Register 10-26: RPINR27: Peripheral Pin Select Input Register 27

        178
      • Register 10-27: RPINR28: Peripheral Pin Select Input Register 28

        178
      • Register 10-28: RPINR29: Peripheral Pin Select Input Register 29

        179
      • Register 10-29: RPOR0: Peripheral Pin Select Output Register 0

        180
      • Register 10-30: RPOR1: Peripheral Pin Select Output Register 1

        180
      • Register 10-31: RPOR2: Peripheral Pin Select Output Register 2

        181
      • Register 10-32: RPOR3: Peripheral Pin Select Output Register 3

        181
      • Register 10-33: RPOR4: Peripheral Pin Select Output Register 4

        182
      • Register 10-34: RPOR5: Peripheral Pin Select Output Register 5

        182
      • Register 10-35: RPOR6: Peripheral Pin Select Output Register 6

        183
      • Register 10-36: RPOR7: Peripheral Pin Select Output Register 7

        183
      • Register 10-37: RPOR8: Peripheral Pin Select Output Register 8

        184
      • Register 10-38: RPOR9: Peripheral Pin Select Output Register 9

        184
      • Register 10-39: RPOR10: Peripheral Pin Select Output Register 10

        185
      • Register 10-40: RPOR11: Peripheral Pin Select Output Register 11

        185
      • Register 10-41: RPOR12: Peripheral Pin Select Output Register 12

        186
      • Register 10-42: RPOR13: Peripheral Pin Select Output Register 13

        186
      • Register 10-43: RPOR14: Peripheral Pin Select Output Register 14

        187
      • Register 10-44: RPOR15: Peripheral Pin Select Output Register 15(1)

        187
• 11.0 Timer1

  189
  • FIGURE 11-1: 16-bit Timer1 Module Block Diagram

    189
  • Register 11-1: T1CON: Timer1 Control Register(1)

    190
• 12.0 Timer2/3 and Timer4/5

  191
  • FIGURE 12-1: Timer2/3 and Timer4/5 (32-bit) Block Diagram

    192
  • FIGURE 12-2: Timer2 and Timer4 (16-bit Synchronous) Block Diagram

    193
  • FIGURE 12-3: Timer3 and Timer5 (16-bit Asynchronous) Block Diagram

    193
  • Register 12-1: TxCON: Timer2 and Timer4 Control Register(3)

    194
  • Register 12-2: TyCON: Timer3 and Timer5 Control Register(3)

    195
• 13.0 Input Capture with Dedicated Timers

  197
  • 13.1 General Operating Modes

    197
    • 13.1.1 Synchronous and Trigger modes

      197
      • FIGURE 13-1: Input Capture Block Diagram

        197
    • 13.1.2 Cascaded (32-bit) Mode

      198
  • 13.2 Capture Operations

    198
    • Register 13-1: ICxCON1: Input Capture x Control Register 1

      199
    • Register 13-2: ICxCON2: Input Capture x Control Register 2

      200
• 14.0 Output Compare with Dedicated Timers

  201
  • 14.1 General Operating Modes

    201
    • 14.1.1 Synchronous and Trigger modes

      201
    • 14.1.2 Cascaded (32-bit) Mode

      201
      • FIGURE 14-1: Output Compare Block Diagram (16-bit Mode)

        202
  • 14.2 Compare Operations

    202
  • 14.3 Pulse-Width Modulation (PWM) Mode

    203
    • FIGURE 14-2: Output Compare Block Diagram (Double-Buffered, 16-bit PWM Mode)

      204
    • 14.3.1 PWM Period

      204
      • EQUATION 14-1: Calculating the PWM Period(1)

        204
    • 14.3.2 PWM Duty Cycle

      205
      • EQUATION 14-2: Calculation for Maximum PWM Resolution(1)

        205
      • EXAMPLE 14-1: PWM Period and Duty Cycle Calculations(1)

        205
      • TABLE 14-1: Example PWM Frequencies and Resolutions at 4 MIPS (Fcy = 4 MHz)(1)

        205
      • TABLE 14-2: Example PWM Frequencies and Resolutions at 16 MIPS (Fcy = 16 MHz)(1)

        205
      • Register 14-1: OCxCON1: Output Compare x Control Register 1

        206
      • Register 14-2: OCxCON2: Output Compare x Control Register 2

        208
• 15.0 Serial Peripheral Interface (SPI)

  211
  • FIGURE 15-1: SPIx Module Block Diagram (Standard Mode)

    212
  • FIGURE 15-2: SPIx Module Block Diagram (Enhanced Mode)

    213
  • Register 15-1: SPIxSTAT: SPIx Status and Control Register

    214
  • Register 15-2: SPIxCON1: SPIx Control Register 1

    216
  • Register 15-3: SPIxCON2: SPIx Control Register 2

    218
  • FIGURE 15-3: SPI Master/Slave Connection (Standard Mode)

    219
  • FIGURE 15-4: SPI Master/Slave Connection (Enhanced Buffer Modes)

    219
  • FIGURE 15-5: SPI Master, Frame Master Connection Diagram

    220
  • FIGURE 15-6: SPI Master, Frame Slave Connection Diagram

    220
  • FIGURE 15-7: SPI Slave, Frame Master Connection Diagram

    220
  • FIGURE 15-8: SPI Slave, Frame Slave Connection Diagram

    220
  • EQUATION 15-1: Relationship Between Device and SPI Clock Speed(1)

    221
  • TABLE 15-1: Sample SCKx Frequencies(1,2)

    221
• 16.0 Inter-Integrated Circuit™ (I2C™)

  223
  • 16.1 Communicating as a Master in a Single Master Environment

    223
    • FIGURE 16-1: I2C™ Block Diagram

      224
  • 16.2 Setting Baud Rate When Operating as a Bus Master

    225
    • EQUATION 16-1: Computing Baud Rate Reload Value(1,2)

      225
  • 16.3 Slave Address Masking

    225
    • TABLE 16-1: I2C™ Clock Rates(1,2)

      225
    • TABLE 16-2: I2C™ reserved addresses(1)

      225
    • Register 16-1: I2CxCON: I2Cx Control Register

      226
    • Register 16-2: I2CxSTAT: I2Cx Status Register

      228
    • Register 16-3: I2CxMSK: I2Cx Slave Mode Address Mask Register

      230
• 17.0 Universal Asynchronous Receiver Transmitter (UART)

  231
  • FIGURE 17-1: UART Simplified Block Diagram

    231
  • 17.1 UART Baud Rate Generator (BRG)

    232
    • EQUATION 17-1: UART Baud Rate with BRGH = 0(1,2)

      232
    • EQUATION 17-2: UART Baud Rate with BRGH = 1(1,2)

      232
    • EXAMPLE 17-1: Baud Rate Error Calculation (BRGH = 0)(1)

      232
  • 17.2 Transmitting in 8-Bit Data Mode

    233
  • 17.3 Transmitting in 9-Bit Data Mode

    233
  • 17.4 Break and Sync Transmit Sequence

    233
  • 17.5 Receiving in 8-Bit or 9-Bit Data Mode

    233
  • 17.6 Operation of UxCTS and UxRTS Control Pins

    233
  • 17.7 Infrared Support

    233
    • 17.7.1 IrDA Clock Output for External IrDA Support

      233
    • 17.7.2 Built-in IrDA Encoder and Decoder

      233
      • Register 17-1: UxMODE: UARTx Mode Register

        234
      • Register 17-2: UxSTA: UARTx Status and Control Register

        236
• 18.0 Universal Serial Bus with On-The-Go Support (USB OTG)

  239
  • TABLE 18-1: Controller-Centric Data Direction for USB Host or Target

    239
  • FIGURE 18-1: USB OTG Module Block Diagram

    240
  • 18.1 Hardware Configuration

    241
    • 18.1.1 Device Mode

      241
      • FIGURE 18-2: External Pull-Up for Full-Speed Device Mode

        241
      • FIGURE 18-3: Bus Power Only

        241
      • FIGURE 18-4: Self-power Only

        241
      • FIGURE 18-5: Dual Power Example

        241
    • 18.1.2 Host and OTG Modes

      242
      • FIGURE 18-6: Host Interface Example

        242
      • FIGURE 18-7: OTG Interface Example

        242
    • 18.1.3 Using An External Interface

      243
    • 18.1.4 Calculating Transceiver Power Requirements

      243
      • EQUATION 18-1: Estimating USB Transceiver Current Consumption

        243
  • 18.2 USB Buffer Descriptors and the BDT

    244
    • FIGURE 18-8: BDT Mapping for Endpoint Buffering Modes

      244
    • 18.2.1 Buffer Ownership

      245
    • 18.2.2 DMA Interface

      245
      • TABLE 18-2: Assignment of Buffer Descriptors for the Different Buffering Modes

        245
      • Register 18-1: BDnSTAT: Buffer Descriptor n Status Register Prototype, USB Mode (BD0STAT through BD63STAT)

        246
      • Register 18-2: BDnSTAT: Buffer Descriptor n Status Register Prototype, CPU Mode (BD0STAT Through BD63STAT)

        247
  • 18.3 USB Interrupts

    248
    • FIGURE 18-9: USB OTG Interrupt Funnel

      248
    • 18.3.1 Clearing USB OTG Interrupts

      249
      • FIGURE 18-10: Example of a USB Transaction and Interrupt Events

        249
  • 18.4 Device Mode Operation

    249
    • 18.4.1 Enabling device mode

      249
    • 18.4.2 Receiving an IN token in device mode

      250
    • 18.4.3 Receiving an OUT token in device mode

      250
  • 18.5 Host Mode Operation

    250
    • 18.5.1 Enable Host Mode and Discover a Connected Device

      250
    • 18.5.2 Complete a Control Transaction to a Connected Device

      251
    • 18.5.3 Send a Full-Speed Bulk Data Transfer to a Target Device

      252
  • 18.6 OTG Operation

    252
    • 18.6.1 Session Request Protocol (SRP)

      252
    • 18.6.2 Host Negotiation Protocol (HNP)

      253
    • 18.6.3 EXTERNAL Vbus COMPARATORS

      253
      • TABLE 18-3: EXTERNAL Vbus COMPARATOR STATES

        253
  • 18.7 USB OTG Module Registers

    254
    • 18.7.1 USB OTG Module Control Registers

      255
      • Register 18-3: U1OTGSTAT: USB OTG Status Register (Host Mode Only)

        255
      • Register 18-4: U1OTGCON: USB On-the-Go Control Register

        256
      • Register 18-5: U1PWRC: USB Power Control Register

        257
      • Register 18-6: U1STAT: USB Status Register

        258
      • Register 18-7: U1CON: USB Control Register (Device Mode)

        259
      • Register 18-8: U1CON: USB Control Register (Host Mode Only)

        260
      • Register 18-9: U1ADDR: USB Address Register

        261
      • Register 18-10: U1TOK: USB Token Register (Host Mode Only)

        261
      • Register 18-11: U1SOF: USB OTG Start-of-token Threshold Register (Host Mode Only)

        262
      • Register 18-12: U1CNFG1: USB Configuration Register 1

        262
      • Register 18-13: U1CNFG2: USB Configuration Register 2

        263
    • 18.7.2 USB Interrupt Registers

      264
      • Register 18-14: U1OTGIR: USB OTG Interrupt Status Register (Host mode Only)

        264
      • Register 18-15: U1OTGIE: USB OTG Interrupt Enable Register (Host Mode Only)

        265
      • Register 18-16: U1IR: USB Interrupt Status Register (Device Mode Only)

        266
      • Register 18-17: U1IR: USB Interrupt Status Register (Host Mode Only)

        267
      • Register 18-18: U1IE: USB Interrupt Enable Register (All USB Modes)

        268
      • Register 18-19: U1EIR: USB Error Interrupt Status Register

        269
      • Register 18-20: U1EIE: USB Error Interrupt Enable Register

        270
    • 18.7.3 USB Endpoint Management Registers

      271
      • Register 18-21: U1EPn: USB Endpoint n Control Registers (n = 0 to 15)

        271
    • 18.7.4 USB Vbus Power Control Register

      272
      • Register 18-22: U1PWMCON: USB Vbus PWM Generator Control Register

        272
• 19.0 Enhanced Parallel Master Port (EPMP)

  273
  • 19.1 ALTPMP Setting

    273
    • TABLE 19-1: Alternate EPMP Pins

      273
    • TABLE 19-2: Parallel Master Port Pin Description

      274
    • Register 19-1: PMCON1: EPMP Control Register 1

      275
    • Register 19-2: PMCON2: EPMP Control Register 2

      276
    • Register 19-3: PMCON3: EPMP Control Register 3

      277
    • Register 19-4: PMCON4: EPMP Control Register 4

      278
    • Register 19-5: PMCSxCF: Chip Select x Configuration Register

      279
    • Register 19-6: PMCSxBS: Chip Select x Base Address Register

      280
    • Register 19-7: PMCSxMD: Chip Select x Mode Register

      281
    • Register 19-8: PMSTAT: EPMP Status Register (Slave mode only)

      282
    • Register 19-9: PADCFG1: Pad Configuration Control Register

      283
• 20.0 Real-Time Clock and Calendar (RTCC)

  285
  • FIGURE 20-1: RTCC Block Diagram

    285
  • 20.1 RTCC Module Registers

    286
    • 20.1.1 Register Mapping

      286
      • TABLE 20-1: RTCVAL Register Mapping

        286
      • TABLE 20-2: ALRMVAL Register Mapping

        286
    • 20.1.2 Write Lock

      286
      • EXAMPLE 20-1: Setting the RTCWREN Bit

        286
    • 20.1.3 RTCC Control Registers

      287
      • Register 20-1: RCFGCAL: RTCC Calibration and Configuration Register(1)

        287
      • Register 20-2: PADCFG1: Pad Configuration Control Register

        288
      • Register 20-3: ALCFGRPT: Alarm Configuration Register

        289
    • 20.1.4 RTCVAL Register Mappings

      290
      • Register 20-4: YEAR: Year Value Register(1)

        290
      • Register 20-5: MTHDY: Month and Day Value Register(1)

        290
      • Register 20-6: WKDYHR: Weekday and Hours Value Register(1)

        291
      • Register 20-7: MINSEC: Minutes and Seconds Value Register

        291
    • 20.1.5 ALRMVAL Register Mappings

      292
      • Register 20-8: ALMTHDY: Alarm Month and Day Value Register(1)

        292
      • Register 20-9: ALWDHR: Alarm Weekday and Hours Value Register(1)

        293
      • Register 20-10: ALMINSEC: Alarm Minutes and Seconds Value Register

        293
  • 20.2 Calibration

    294
    • EQUATION 20-1: RTCC Calibration

      294
  • 20.3 Alarm

    294
    • 20.3.1 Configuring the Alarm

      294
    • 20.3.2 Alarm Interrupt

      294
      • FIGURE 20-2: Alarm Mask Settings

        295
• 21.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator

  297
  • FIGURE 21-1: CRC Block Diagram

    297
  • FIGURE 21-2: CRC Shift Engine Detail

    297
  • 21.1 User Interface

    298
    • 21.1.1 Polynomial Interface

      298
      • EQUATION 21-1: 16-Bit, 32-bit CRC Polynomials

        298
    • 21.1.2 DATA INTERFACE

      298
      • TABLE 21-1: CRC SETUP EXAMPLES FOR 16 AND 32-BIT POLYNOMIALs

        298
    • 21.1.3 Data Shift Direction

      299
    • 21.1.4 Interrupt Operation

      299
    • 21.1.5 Typical Operation

      299
      • Register 21-1: CRCCON1: CRC Control 1 Register

        300
      • Register 21-2: CRCCON2: CRC Control 2 Register

        301
      • Register 21-3: CRCXORL: CRC XOR POLYNOMIAL REGISTER, LOW BYTE

        301
      • Register 21-4: CRCXORH: CRC XOR High Register

        302
      • Register 21-5: CRCDATL: CRC Data Low Register

        302
      • Register 21-6: CRCDATH: CRC Data High Register

        302
      • Register 21-7: CRCWDATL: CRC Shift Low Register

        303
      • Register 21-8: CRCWDATH: CRC Shift High Register

        303
• 22.0 Graphics Controller Module (GFX)

  305
  • FIGURE 22-1: Graphics Module Overview

    305
  • 22.1 GFX Module Registers

    306
    • Register 22-1: G1CMDL: GPU COMMAND LOW REGISTER

      306
    • Register 22-2: G1CMDH: GPU COMMAND HIGH REGISTER

      306
    • Register 22-3: G1CON1: DISPLAY CONTROL REGISTER 1

      307
    • Register 22-4: G1CON2: DISPLAY CONTROL REGISTER 2

      308
    • Register 22-5: G1CON3: DISPLAY CONTROL REGISTER 3

      309
    • Register 22-6: G1STAT: GFX Status REGISTER

      310
    • Register 22-7: G1IE: GFX INTERRUPT ENABLE REGISTER

      311
    • Register 22-8: G1IR: GFX INTERRUPT STATUS REGISTER

      312
    • Register 22-9: G1W1ADRL: GPU WORK AREA 1 START ADDRESS REGISTER LOW

      313
    • Register 22-10: G1W1ADRH: GPU WORK AREA 1 START ADDRESS REGISTER HIGH

      313
    • Register 22-11: G1W2ADRL: GPU WORK AREA 2 START ADDRESS REGISTER LOW

      313
    • Register 22-12: G1W2ADRH: GPU WORK AREA 2 START ADDRESS REGISTER HIGH

      314
    • Register 22-13: G1PUW: GPU WORK AREA WIDTH REGISTER

      314
    • Register 22-14: G1PUH: GPU WORK AREA HEIGHT REGISTER

      314
    • Register 22-15: G1DPADRL: DISPLAY BUFFER START ADDRESS REGISTER LOW

      315
    • Register 22-16: G1DPADRH: DISPLAY BUFFER START ADDRESS REGISTER HIGH

      315
    • Register 22-17: G1DPW: DISPLAY Buffer WIDTH REGISTER

      315
    • Register 22-18: G1DPH: DISPLAY Buffer HEIGHT REGISTER

      316
    • Register 22-19: G1DPWT: DISPLAY TOTAL WIDTH REGISTER

      316
    • Register 22-20: G1DPHT: DISPLAY TOTAL HEIGHT REGISTER

      316
    • Register 22-21: G1ACTDA: ACTIVE DISPLAY AREA REGISTER

      317
    • Register 22-22: G1HSYNC: HORIZONTAL SYNCHRONIZATION CONTROL REGISTER

      317
    • Register 22-23: G1VSYNC: VERTICAL SYNCHRONIZATION CONTROL REGISTER

      318
    • Register 22-24: G1DBLCON: DISPLAY BLANKING CONTROL REGISTER

      318
    • Register 22-25: G1CLUT: COLOR LOOK-UP TABLE CONTROL REGISTER

      319
    • Register 22-26: G1CLUTWR: COLOR LOOK-UP TABLE (CLUT) Memory WRITE DATA REGISTER

      320
    • Register 22-27: G1CLUTRD: COLOR LOOK-UP TABLE (CLUT) MEMORY READ DATA REGISTER

      320
    • Register 22-28: G1MRGN: INTERRUPT ADVANCE REGISTER

      321
    • Register 22-29: G1CHRX: CHARACTER-X COORDINATE PRINT POSITION REGISTER

      321
    • Register 22-30: G1CHRY: CHARACTER Y-COORDINATE PRINT POSITION REGISTER

      322
    • Register 22-31: G1IPU: INFLATE PROCESSOR STATUS REGISTER

      322
    • Register 22-32: G1DBEN: DATA I/O PAD ENABLE REGISTER

      323
  • 22.2 Display Resolution and Memory Requirements

    324
  • 22.3 Display Clock (GCLK) Source

    324
  • 22.4 Display Buffer and Work Areas Memory Locations

    324
    • TABLE 22-1: Buffer Memory Requirements vs. Display Configuration

      324
• 23.0 10-Bit High-Speed A/D Converter

  325
  • FIGURE 23-1: 10-Bit High-Speed A/D Converter Block Diagram

    326
  • Register 23-1: AD1CON1: A/D Control Register 1

    327
  • Register 23-2: AD1CON2: A/D Control Register 2

    328
  • Register 23-3: AD1CON3: A/D Control Register 3

    329
  • Register 23-4: AD1CHS: A/D Input Select Register

    330
  • Register 23-5: ANCFG: A/D Band gap Reference Configuration Register

    331
  • Register 23-6: AD1CSSL: A/D Input Scan Select Register (Low)

    331
  • Register 23-7: AD1CSSH: A/D Input Scan Select Register (High)

    332
  • EQUATION 23-1: A/D Conversion Clock Period(1)

    332
  • FIGURE 23-2: 10-bit A/D Converter Analog Input Model

    333
  • FIGURE 23-3: A/D Transfer Function

    333
• 24.0 Triple Comparator Module

  335
  • FIGURE 24-1: Triple Comparator Module Block Diagram

    335
  • FIGURE 24-2: Individual Comparator Configurations when CREF = 0

    336
  • FIGURE 24-3: Individual Comparator Configurations when CREF = 1 and CVREFP = 0

    337
  • FIGURE 24-4: Individual Comparator Configurations when CREF = 1 and CVREFP = 1

    337
  • Register 24-1: CMxCON: Comparator x Control Registers (Comparators 1 Through 3)

    338
  • Register 24-2: CMSTAT: Comparator Module Status Register

    339
• 25.0 Comparator Voltage Reference

  341
  • 25.1 Configuring the Comparator Voltage Reference

    341
    • FIGURE 25-1: Comparator Voltage Reference Block Diagram

      341
    • Register 25-1: CVRCON: Comparator Voltage Reference Control Register

      342
• 26.0 Charge Time Measurement Unit (CTMU)

  343
  • 26.1 Measuring Capacitance

    343
    • FIGURE 26-1: Typical Connections and Internal Configuration for Capacitance Measurement

      343
  • 26.2 Measuring Time

    344
  • 26.3 Pulse Generation and Delay

    344
    • FIGURE 26-2: Typical Connections and Internal Configuration for Time Measurement Time

      344
    • FIGURE 26-3: Typical Connections and Internal Configuration for Pulse Delay Generation

      344
    • Register 26-1: CTMUCON: CTMU Control Register

      345
    • Register 26-2: CTMUICON: CTMU current Control Register

      346
• 27.0 Special Features

  347
  • 27.1 Configuration Bits

    347
    • 27.1.1 Considerations for Configuring PIC24FJ256DA210 family Devices

      347
      • TABLE 27-1: Flash Configuration Word Locations for PIC24FJ256DA210 family Devices

        347
      • Register 27-1: CW1: Flash Configuration Word 1

        348
      • Register 27-2: CW2: Flash Configuration Word 2

        350
      • Register 27-3: CW3: Flash Configuration Word 3

        351
      • Register 27-4: CW4: Flash Configuration Word 4

        352
      • Register 27-5: DEVID: Device ID Register

        353
      • Register 27-6: DEVREV: Device Revision Register

        354
  • 27.2 On-Chip Voltage Regulator

    354
    • 27.2.1 Voltage Regulator Low-Voltage Detection

      354
      • FIGURE 27-1: Connections for the On-Chip Regulator

        354
    • 27.2.2 On-Chip Regulator and POR

      354
    • 27.2.3 On-Chip Regulator and BOR

      355
    • 27.2.4 Voltage Regulator Standby Mode

      355
  • 27.3 Watchdog Timer (WDT)

    355
    • 27.3.1 Windowed Operation

      356
    • 27.3.2 Control Register

      356
      • FIGURE 27-2: WDT Block Diagram

        356
  • 27.4 Program Verification and Code Protection

    357
    • 27.4.1 General Segment Protection

      357
    • 27.4.2 Code Segment Protection

      357
    • 27.4.3 Configuration Register Protection

      358
      • TABLE 27-2: Code Segment Protection Configuration Options

        358
  • 27.5 JTAG Interface

    358
  • 27.6 In-Circuit Serial Programming™

    358
  • 27.7 In-Circuit Debugger

    358
• 28.0 Development Support

  359
  • 28.1 MPLAB Integrated Development Environment Software

    359
  • 28.2 MPLAB C Compilers for Various Device Families

    360
  • 28.3 HI-TECH C for Various Device Families

    360
  • 28.4 MPASM Assembler

    360
  • 28.5 MPLINK Object Linker/ MPLIB Object Librarian

    360
  • 28.6 MPLAB Assembler, Linker and Librarian for Various Device Families

    360
  • 28.7 MPLAB SIM Software Simulator

    361
  • 28.8 MPLAB REAL ICE In-Circuit Emulator System

    361
  • 28.9 MPLAB ICD 3 In-Circuit Debugger System

    361
  • 28.10 PICkit 3 In-Circuit Debugger/Programmer and PICkit 3 Debug Express

    361
  • 28.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express

    362
  • 28.12 MPLAB PM3 Device Programmer

    362
  • 28.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits

    362
• 29.0 Instruction Set Summary

  363
  • TABLE 29-1: Symbols Used in Opcode Descriptions

    364
  • TABLE 29-2: Instruction Set Overview

    365
• 30.0 Electrical Characteristics

  371
  • Absolute Maximum Ratings(†)

    371
  • 30.1 DC Characteristics

    372
    • FIGURE 30-1: PIC24FJ256DA210 family Voltage-Frequency Graph (Industrial)

      372
    • TABLE 30-1: Thermal Operating Conditions

      372
    • TABLE 30-2: Thermal Packaging Characteristics

      372
    • TABLE 30-3: DC Characteristics: Temperature and Voltage Specifications

      373
    • TABLE 30-4: DC Characteristics: Operating Current (Idd)

      374
    • TABLE 30-5: DC Characteristics: Idle Current (Iidle)

      375
    • TABLE 30-6: DC Characteristics: Power-Down Current (Ipd)

      376
    • TABLE 30-7: DC Characteristics: I/O Pin Input Specifications

      377
    • TABLE 30-8: DC Characteristics: I/O Pin Output Specifications

      378
    • TABLE 30-9: DC Characteristics: Program Memory

      378
    • TABLE 30-10: Internal Voltage Regulator Specifications

      379
  • 30.2 AC Characteristics and Timing Parameters

    379
    • TABLE 30-11: Temperature and Voltage Specifications – AC

      379
    • FIGURE 30-2: Load Conditions for Device Timing Specifications

      379
    • TABLE 30-12: Capacitive Loading Requirements on Output Pins

      380
    • FIGURE 30-3: External Clock Timing

      380
    • TABLE 30-13: External Clock Timing Requirements

      381
    • TABLE 30-14: PLL Clock Timing Specifications (Vdd = 2.2V to 3.6V)

      381
    • TABLE 30-15: Internal RC Accuracy

      382
    • TABLE 30-16: RC Oscillator Start-Up Time

      382
    • TABLE 30-17: Reset and Brown-out Reset Requirements

      382
    • FIGURE 30-4: CLKO and I/O Timing Characteristics

      383
    • TABLE 30-18: CLKO and I/O Timing Requirements

      383
    • TABLE 30-19: ADC Module Specifications

      384
    • TABLE 30-20: ADC Conversion Timing Requirements(1)

      385
• 31.0 Packaging Information

  387
  • 31.1 Package Marking Information

    387
  • 31.2 Package Details

    388
• Appendix A: Revision History

  397
  • Revision A (February 2010)

    397
  • Revision B (May 2010)

    397
• INDEX

  399
• The Microchip Web Site

  405
• Customer Change Notification Service

  405
• Customer Support

  405
• Reader Response

  406
• Product Identification System

  407
• Worldwide Sales and Service

  408