Microchip Technology AC164139 Data Sheet
PIC24FJ256DA210 FAMILY
DS39969B-page 146
2010 Microchip Technology Inc.
bit 5
PLLEN: 96 MHz PLL Enable bit
The 96 MHz PLL must be enabled when the USB or graphics controller module is enabled. This control
bit can be overridden by the PLL96MHZ (Configuration Word 2 <11>) Configuration bit.
1
The 96 MHz PLL must be enabled when the USB or graphics controller module is enabled. This control
bit can be overridden by the PLL96MHZ (Configuration Word 2 <11>) Configuration bit.
1
= Enable the 96 MHz PLL for USB, graphics controller or HSPLL/ECPLL/FRCPLL operation
0
= Disable the 96 MHz PLL
bit 4
G1CLKSEL: Display Controller Module Clock Select bit
1
= Use the 96 MHz clock as a graphics controller module clock
0
= Use the 48 MHz clock as a graphics controller module clock
bit 3-0
Unimplemented: Read as ‘0’
REGISTER 8-2:
CLKDIV: CLOCK DIVIDER REGISTER (CONTINUED)
Note 1:
This bit is automatically cleared when the ROI bit is set and an interrupt occurs.
2:
This setting is not allowed while the USB module is enabled.
REGISTER 8-3:
OSCTUN: FRC OSCILLATOR TUNE REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
TUN5
(1)
TUN4
(1)
TUN3
(1)
TUN2
(1)
TUN1
(1)
TUN0
(1)
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-6
Unimplemented: Read as ‘0’
bit 5-0
TUN<5:0>: FRC Oscillator Tuning bits
(1)
011111
= Maximum frequency deviation
011110
=
·
·
·
000001
·
·
000001
=
000000
= Center frequency, oscillator is running at factory calibrated frequency
111111
=
·
·
·
100001
·
·
100001
=
100000
= Minimum frequency deviation
Note 1:
Increments or decrements of TUN<5:0> may not change the FRC frequency in equal steps over the FRC
tuning range and may not be monotonic.
tuning range and may not be monotonic.