Microchip Technology AC164139 Data Sheet
PIC24FJ256DA210 FAMILY
DS39969B-page 192
2010 Microchip Technology Inc.
FIGURE 12-1:
TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM
TMR3
TMR2
Set T3IF (T5IF)
Equal
Comparator
PR3
PR2
Reset
LSB
MSB
Note 1:
The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are
respective to the T2CON and T4CON registers.
respective to the T2CON and T4CON registers.
2:
The timer clock input must be assigned to an available RPn/RPIn
pin before use. See Section 10.4 “Peripheral
Pin Select (PPS)” for more information.
3:
The ADC event trigger is available only on Timer 2/3 in 32-bit mode and Timer 3 in 16-bit mode.
Data Bus<15:0>
TMR3HLD
Read TMR2 (TMR4)
(1)
Write TMR2 (TMR4)
(1)
16
16
16
Q
Q
D
CK
TGATE
0
1
TON
TCKPS<1:0>
Prescaler
1, 8, 64, 256
2
T
CY
TCS
(2)
TGATE
(2)
Gate
T2CK
Sync
ADC Event Trigger
(3)
Sync
(T4CK)
(PR5)
(PR4)
(TMR5HLD)
(TMR5)
(TMR4)
1x
01
00