Microchip Technology AC164139 Data Sheet
2010 Microchip Technology Inc.
DS39969B-page 309
PIC24FJ256DA210 FAMILY
REGISTER 22-5:
G1CON3: DISPLAY CONTROL REGISTER 3
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
DPPINOE
DPPOWER
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DPCLKPOL
DPENPOL
DPVSPOL
DPHSPOL
DPPWROE
DPENOE
DPVSOE
DPHSOE
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-10
Unimplemented: Read as ‘0’
bit 9
DPPINOE: Display Pin Output Pad Enable bit
DPPINOE is the master output enable and must be set to allow GDBEN<15:0>, DPENOE,
DPPWROE, DPVSOE and DPHSOE to enable the associated pads
1
DPPINOE is the master output enable and must be set to allow GDBEN<15:0>, DPENOE,
DPPWROE, DPVSOE and DPHSOE to enable the associated pads
1
= Enable display output pads
0
= Disable display output signals as set by GDBEN<15:0>
Pins used by the signals are assigned to the next enabled module that uses the same pins.
For data signals, GDBEN<15:0> can be used to disable or enable specific data signals while
DPPINOE is set.
For data signals, GDBEN<15:0> can be used to disable or enable specific data signals while
DPPINOE is set.
bit 8
DPPOWER: Display Power-up Power-Down Sequencer Control bit
Refer to the “PIC24F Family Reference Manual”, Section 43. “Graphics Controller Module (GFX)”
for details.
1
Refer to the “PIC24F Family Reference Manual”, Section 43. “Graphics Controller Module (GFX)”
for details.
1
= Set Display Power Sequencer Control port (GPWR) to ‘1’
0
= Set Power Control Sequencer signal (GPWR) ‘0’
bit 7
DPCLKPOL: Display Glass Clock (GCLK) Polarity bit
1
= Display latches data on the positive edge of GCLK
0
= Display latches data on the negative edge of GCLK
bit 6
DPENPOL: Display Enable Signal (GEN) Polarity bit
For TFT mode (DPMODE (G1CON2<2:0>) = 001):
1
For TFT mode (DPMODE (G1CON2<2:0>) = 001):
1
= Active-high (GEN)
0
= Active-low (GEN)
For STN mode (DPMODE (G1CON2<2:0>) = 010 or 011):
1
1
= GEN connects to the shift clock input of the display (Shift Clock mode)
0
= GEN connects to the MOD input of the display (Line/Frame Toggle mode)
bit 5
DPVSPOL: Display Vertical Synchronization (V
SYNC
) Polarity bit
1
= Active-high (V
SYNC
)
0
= Active-low (V
SYNC
)
bit 4
DPHSPOL: Display Horizontal Synchronization (HSYNC) Polarity bit
1
= Active-high (HSYNC)
0
= Active-low (HSYNC)
bit 3
DPPWROE: Display Power-up/Power-Down Sequencer Control port (GPWR) enable bit
1
= GPWR port is enabled (pin controlled by the DPPOWER bit (G1CON3<8>))
0
= GPWR port is disabled (pin can be used as an ordinary I/O)
bit 2
DPENOE: Display Enable Port Enable bit
1
= GEN port is enabled
0
= GEN port is disabled