Microchip Technology AC164139 Data Sheet

 2010 Microchip Technology Inc.

DS39969B-page 355

27.2.3

ON-CHIP REGULATOR AND BOR

When the on-chip regulator is enabled,
PIC24FJ256DA210 family devices also have a simple
brown-out capability. If the voltage supplied to the reg-
ulator is inadequate to maintain the output level, the
regulator Reset circuitry will generate a Brown-out
Reset. This event is captured by the BOR (RCON<1>)
flag bit. The brown-out voltage specifications are
provided in Section 7. “Reset” (DS39712) in the
“PIC24F Family Reference Manual”. 

27.2.4

VOLTAGE REGULATOR STANDBY 
MODE

When enabled, the on-chip regulator always consumes
a small incremental amount of current over I

DD

/I

PD

,

including when the device is in Sleep mode, even
though the core digital logic does not require power. To
provide additional savings in applications where power
resources are critical, the regulator can be made to
enter Standby mode on its own whenever the device
goes into Sleep mode. This feature is controlled by the
VREGS bit (RCON<8>). Clearing the VREGS bit
enables the Standby mode. When waking up from
Standby mode, the regulator needs to wait for T

VREG

 to

expire before wake-up.
The regulator wake-up time required for Standby
mode is controlled by the WUTSEL<1:0>
(CW3<11:10>) Configuration bits. The regulator
wake-up time is lower when WUTSEL<1:0> = 01, and
higher when WUTSEL<1:0> = 11. Refer to the T

VREG

specification in Table 30-10 for regulator wake-up
time.
When the regulator’s Standby mode is turned off
(VREGS = 1), the device wakes up without waiting for
TV

REG

. However, with the VREGS bit set, the power

consumption while in Sleep mode will be approximately
40 

A higher than what it would be if the regulator was

allowed to enter Standby mode.

For PIC24FJ256DA210 family devices, the WDT is
driven by the LPRC oscillator. When the WDT is
enabled, the clock source is also enabled.
The nominal WDT clock source from LPRC is 31 kHz.
This feeds a prescaler that can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the FWPSA Configuration bit.
With a 31 kHz input, the prescaler yields a nominal
WDT Time-out period (T

WDT

) of 1 ms in 5-bit mode or

4 ms in 7-bit mode.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPS<3:0> Con-
figuration bits (CW1<3:0>), which allows the selection
of a total of 16 settings, from 1:1 to 1:32,768. Using the
prescaler and postscaler time-out periods, ranging
from 1 ms to 131 seconds, can be achieved.
The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether 

invoked by software (i.e., setting the OSWEN bit 
after changing the NOSC bits) or by hardware 
(i.e., Fail-Safe Clock Monitor)

• When a PWRSAV instruction is executed 

(i.e., Sleep or Idle mode is entered)

• When the device exits Sleep or Idle mode to 

resume normal operation

• By  a  CLRWDT instruction during normal execution
If the WDT is enabled, it will continue to run during
Sleep or Idle modes. When the WDT time-out occurs,
the device will wake the device and code execution will
continue from where the PWRSAV instruction was exe-
cuted. The corresponding SLEEP or IDLE
(RCON<3:2>) bits will need to be cleared in software
after the device wakes up. 
The WDT Flag bit, WDTO (RCON<4>), is not auto-
matically cleared following a WDT time-out. To detect
subsequent WDT events, the flag must be cleared in
software.  

For more information, see Section 30.0
“Electrical Characteristics”.  The infor-
mation in this data sheet supersedes the
information in the FRM.

The  CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.