Microchip Technology AC164139 Data Sheet
2010 Microchip Technology Inc.
DS39969B-page 45
PIC24FJ256DA210 FAMILY
4.0
MEMORY ORGANIZATION
As Harvard architecture devices, PIC24F micro-
controllers feature separate program and data memory
spaces and busses. This architecture also allows direct
access of program memory from the data space during
code execution.
controllers feature separate program and data memory
spaces and busses. This architecture also allows direct
access of program memory from the data space during
code execution.
4.1
Program Memory Space
The program address memory space of the
PIC24FJ256DA210 family devices is 4M instructions.
The space is addressable by a 24-bit value derived
PIC24FJ256DA210 family devices is 4M instructions.
The space is addressable by a 24-bit value derived
from either the 23-bit Program Counter (PC) during pro-
gram execution, or from table operation or data space
remapping, as described in Section 4.3 “Interfacing
Program and Data Memory Spaces”.
User access to the program memory space is restricted
to the lower half of the address range (000000h to
7FFFFFh). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG<7> to permit access to
the Configuration bits and Device ID sections of the
configuration memory space.
Memory maps for the PIC24FJ256DA210 family of
devices are shown in Figure 4-1.
gram execution, or from table operation or data space
remapping, as described in Section 4.3 “Interfacing
Program and Data Memory Spaces”.
User access to the program memory space is restricted
to the lower half of the address range (000000h to
7FFFFFh). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG<7> to permit access to
the Configuration bits and Device ID sections of the
configuration memory space.
Memory maps for the PIC24FJ256DA210 family of
devices are shown in Figure 4-1.
FIGURE 4-1:
PROGRAM SPACE MEMORY MAP FOR PIC24FJ256DA210 FAMILY DEVICES
000000h
0000FEh
000002h
000100h
F8000Eh
F80010h
FEFFFEh
FFFFFEh
000004h
000200h
0001FEh
000104h
Reset Address
DEVID (2)
GOTO
Instruction
Reserved
Alternate Vector Table
Reserved
Interrupt Vector Table
PIC24FJ128DAXXX
C
on
fig
u
rat
ion Mem
or
y
S
pace
U
ser Mem
or
y
S
pace
Flash Config Words
Note:
Memory areas are not shown to scale.
FF0000h
F7FFFEh
F80000h
Device Config Registers
800000h
7FFFFEh
Reserved
02AC00h
02ABFEh
Unimplemented
Read ‘0’
Reset Address
Device Config Registers
User Flash
Program Memory
(87K instructions)
DEVID (2)
GOTO
Instruction
Reserved
Alternate Vector Table
Reserved
Interrupt Vector Table
PIC24FJ256DAXXX
Reserved
Flash Config Words
Unimplemented
Read ‘0’
015800h
0157FEh
User Flash
Program Memory
(44K instructions)
(44K instructions)