Microchip Technology AC164139 Data Sheet
PIC24FJ256DA210 FAMILY
DS39969B-page 76
2010 Microchip Technology Inc.
TABLE 4-36:
PROGRAM SPACE ADDRESS CONSTRUCTION
FIGURE 4-8:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Access Type
Access
Space
Program Space Address
<23>
<22:16>
<15>
<14:1>
<0>
Instruction Access
(Code Execution)
(Code Execution)
User
0
PC<22:1>
0
0xx xxxx xxxx xxxx xxxx xxx0
TBLRD/TBLWT
(Byte/Word Read/Write)
(Byte/Word Read/Write)
User
TBLPAG<7:0>
Data EA<15:0>
0xxx xxxx
xxxx xxxx xxxx xxxx
Configuration TBLPAG<7:0>
Data
EA<15:0>
1xxx xxxx
xxxx xxxx xxxx xxxx
Program Space Visibility
(Block Remap/Read)
(Block Remap/Read)
User
0
DSRPAG<7:0>
(2)
Data EA<14:0>
(1)
0
xxxx xxxx
xxx xxxx xxxx xxxx
Note 1:
Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of
the address is DSRPAG<0>.
the address is DSRPAG<0>.
2:
DSRPAG<9> is always ‘1’ in this case. DSRPAG<8> decides whether the lower word or higher word of
program memory is read. When DSRPAG<8> is ‘0’, the lower word is read and when it is ‘1’, the higher
word is read.
program memory is read. When DSRPAG<8> is ‘0’, the lower word is read and when it is ‘1’, the higher
word is read.
0
Program Counter
23 Bits
1
DSRPAG<7:0>
8 Bits
EA
15 Bits
Program Counter
Select
TBLPAG
8 Bits
EA
16 Bits
Byte Select
0
0
1
/0
User/Configuration
Table Operations
(2)
Program Space Visibility
(1)
Space Select
24 Bits
23 Bits
(Remapping)
1
/0
1
/0
Note 1: DSRPAG<8> acts as word select. DSRPAG<9> should always be ‘1’ to map program memory to data memory.
2: The instructions, TBLRDH/TBLWTH/TBLRDL/TBLWTL, decide if the higher or lower word of program memory is
accessed. TBLRDH/TBLWTH instructions access the higher word and TBLRDL/TBLWTL instructions access the
lower word. Table read operations are permitted in the configuration memory space.
lower word. Table read operations are permitted in the configuration memory space.
1-Bit