Microchip Technology MCP1630DM-DDBS1 Data Sheet

2007 Microchip Technology Inc.

DS41211D-page 9

PIC12F683

TABLE 2-1:

PIC12F683 SPECIAL REGISTERS SUMMARY BANK 0

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Page

Bank 0

00h

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

xxxx xxxx

17, 90

01h

TMR0

Timer0 Module Register

xxxx xxxx

41, 90

02h

PCL

Program Counter’s (PC) Least Significant Byte

0000 0000

17, 90

03h

STATUS

IRP

(1)

RP1

(1)

RP0

0001 1xxx

11, 90

04h

FSR

Indirect Data Memory Address Pointer

xxxx xxxx

17, 90

05h

GPIO

—

GP5

GP4

GP3

GP2

GP1

GP0

--xx xxxx

31, 90

06h

—

Unimplemented

—

07h

—

Unimplemented

—

08h

—

Unimplemented

—

09h

—

Unimplemented

—

0Ah

PCLATH

—

Write Buffer for upper 5 bits of Program Counter

---0 0000

17, 90

0Bh

INTCON

GIE PEIE

T0IE

INTE

GPIE

T0IF

INTF

GPIF

0000 0000

13, 90

0Ch

PIR1

EEIF

ADIF

CCP1IF

—

CMIF

OSFIF

TMR2IF

TMR1IF

000- 0000

15, 90

0Dh

—

Unimplemented

—

0Eh

TMR1L

Holding Register for the Least Significant Byte of the 16-bit TMR1

xxxx xxxx

44, 90

0Fh

TMR1H

Holding Register for the Most Significant Byte of the 16-bit TMR1

xxxx xxxx

44, 90

10h

T1CON

T1GINV

TMR1GE

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

TMR1CS

TMR1ON

0000 0000

47, 90

11h

TMR2

Timer2 Module Register

0000 0000

49, 90

12h

T2CON

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON

T2CKPS1

T2CKPS0

-000 0000

50, 90

13h

CCPR1L

Capture/Compare/PWM Register 1 Low Byte

xxxx xxxx

76, 90

14h

CCPR1H

Capture/Compare/PWM Register 1 High Byte

xxxx xxxx

76, 90

15h

CCP1CON

—

DC1B1

DC1B0

CCP1M3

CCP1M2

CCP1M1

CCP1M0

--00 0000

75, 90

16h

—

Unimplemented

—

17h

—

Unimplemented

—

18h

WDTCON

—

WDTPS3

WDTPS2

WDTPS1

WDTPS0

SWDTEN

---0 1000

97, 90

19h

CMCON0

—

COUT

—

CINV

CIS

CM2

CM1

CM0

-0-0 0000

56, 90

1Ah

CMCON1

—

T1GSS

CMSYNC

---- --10

57, 90

1Bh

—

Unimplemented

—

1Ch

—

Unimplemented

—

1Dh

—

Unimplemented

—

1Eh

ADRESH

Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result

xxxx xxxx

61,90

1Fh

ADCON0

ADFM

VCFG

—

CHS1

CHS0

GO/DONE

ADON

00-- 0000

65,90

Legend:

– = unimplemented locations read as ‘

’,

= unchanged,

= unknown,

= value depends on condition,

shaded = unimplemented

Note

IRP and RP1 bits are reserved, always maintain these bits clear.