Microchip Technology MCP1630DM-DDBS1 Data Sheet
©
2007 Microchip Technology Inc.
DS41211D-page 11
PIC12F683
2.2.2.1
STATUS Register
The STATUS register, shown in Register 2-1, contains:
• Arithmetic status of the ALU
• Reset status
• Bank select bits for data memory (SRAM)
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example,
CLRF STATUS
, will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as
as
000u u1uu
(where
u
= unchanged).
It is recommended, therefore, that only
BCF, BSF,
SWAPF
and
MOVWF
instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not affect-
ing any Status bits, see the “Instruction Set Summary”.
affect any Status bits. For other instructions not affect-
ing any Status bits, see the “Instruction Set Summary”.
Note 1: Bits IRP and RP1 of the STATUS register
are not used by the PIC12F683 and
should be maintained as clear. Use of
these bits is not recommended, since this
may affect upward compatibility with
future products.
should be maintained as clear. Use of
these bits is not recommended, since this
may affect upward compatibility with
future products.
2: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction.
subtraction.
REGISTER 2-1:
STATUS: STATUS REGISTER
Reserved
Reserved
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
IRP
RP1
RP0
TO
PD
Z
DC
C
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IRP: This bit is reserved and should be maintained as ‘
0
’
bit 6
RP1: This bit is reserved and should be maintained as ‘
0
’
bit 5
RP0: Register Bank Select bit (used for direct addressing)
1
= Bank 1 (80h – FFh)
0
= Bank 0 (00h – 7Fh)
bit 4
TO: Time-out bit
1
= After power-up,
CLRWDT
instruction or
SLEEP
instruction
0
= A WDT time-out occurred
bit 3
PD: Power-down bit
1
= After power-up or by the
CLRWDT
instruction
0
= By execution of the
SLEEP
instruction
bit 2
Z: Zero bit
1
= The result of an arithmetic or logic operation is zero
0
= The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit Carry/Borrow bit (
ADDWF
,
ADDLW,SUBLW,SUBWF
instructions), For Borrow, the polarity is
reversed.
1
= A carry-out from the 4th low-order bit of the result occurred
0
= No carry-out from the 4th low-order bit of the result
bit 0
C: Carry/Borrow bit
(1)
(
ADDWF
,
ADDLW, SUBLW, SUBWF
instructions)
1
= A carry-out from the Most Significant bit of the result occurred
0
= No carry-out from the Most Significant bit of the result occurred
Note 1:
For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (
second operand. For rotate (
RRF
,
RLF
) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.