Microchip Technology MCP1630DM-DDBS1 Data Sheet
©
2007 Microchip Technology Inc.
DS41211D-page 15
PIC12F683
2.2.2.5
PIR1 Register
The PIR1 register contains the interrupt flag bits, as
shown in Register 2-5.
shown in Register 2-5.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User software should ensure the appropri-
ate interrupt flag bits are clear prior to
enabling an interrupt.
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User software should ensure the appropri-
ate interrupt flag bits are clear prior to
enabling an interrupt.
REGISTER 2-5:
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
EEIF
ADIF
CCP1IF
—
CMIF
OSFIF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
EEIF: EEPROM Write Operation Interrupt Flag bit
1
= The write operation completed (must be cleared in software)
0
= The write operation has not completed or has not been started
bit 6
ADIF: A/D Interrupt Flag bit
1
= A/D conversion complete
0
= A/D conversion has not completed or has not been started
bit 5
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1
= A TMR1 register capture occurred (must be cleared in software)
0
= No TMR1 register capture occurred
Compare mode:
1
= A TMR1 register compare match occurred (must be cleared in software)
0
= No TMR1 register compare match occurred
PWM mode:
Unused in this mode
Unused in this mode
bit 4
Unimplemented: Read as ‘
0
’
bit 3
CMIF: Comparator Interrupt Flag bit
1
= Comparator 1 output has changed (must be cleared in software)
0
= Comparator 1 output has not changed
bit 2
OSFIF: Oscillator Fail Interrupt Flag bit
1
= System oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0
= System clock operating
bit 1
TMR2IF: Timer2 to PR2 Match Interrupt Flag bit
1
= Timer2 to PR2 match occurred (must be cleared in software)
0
= Timer2 to PR2 match has not occurred
bit 0
TMR1IF: Timer1 Overflow Interrupt Flag bit
1
= Timer1 register overflowed (must be cleared in software)
0
= Timer1 has not overflowed