Microchip Technology MCP1630DM-DDBS1 Data Sheet
PIC12F683
DS41211D-page 38
©
2007 Microchip Technology Inc.
4.2.5.4
GP3/MCLR/V
PP
Figure 4-4 shows the diagram for this pin. The GP3 pin
is configurable to function as one of the following:
is configurable to function as one of the following:
• a general purpose input
• as Master Clear Reset with weak pull-up
FIGURE 4-4:
BLOCK DIAGRAM OF GP3
4.2.5.5
GP4/AN3/T1G/OSC2/CLKOUT
Figure 4-5 shows the diagram for this pin. The GP4 pin
is configurable to function as one of the following:
is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the ADC
• a Timer1 gate input
• a crystal/resonator connection
• a clock output
FIGURE 4-5:
BLOCK DIAGRAM OF GP4
Input
V
SS
D
Q
CK
Q
D
EN
Q
Data
RD GPIO
RD
WR
IOC
RD
Reset
MCLRE
RD
V
SS
D
EN
Q
MCLRE
V
DD
Weak
MCLRE
Interrupt-on-
change
pin
GPIO
IOC
Bus
TRISIO
Q3
I/O pin
V
DD
V
SS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
V
DD
D
EN
Q
D
EN
Q
Weak
Analog
Input Mode
Data
WR
WPU
RD
WPU
RD
GPIO
WR
GPIO
WR
TRISIO
RD
TRISIO
WR
IOC
RD
IOC
F
OSC
/4
To A/D Converter
Oscillator
Circuit
OSC1
CLKOUT
0
1
CLKOUT
Enable
Enable
Analog
Input Mode
GPPU
RD GPIO
To T1G
INTOSC/
RC/EC
RC/EC
(2)
CLK
(1)
Modes
CLKOUT
Enable
Note 1: CLK modes are XT, HS, LP, optional LP oscillator and
CLKOUT Enable.
2: With CLKOUT option.
Interrupt-on-
change
Bus
Q3