Microchip Technology MCP1630DM-DDBS1 Data Sheet
©
2007 Microchip Technology Inc.
DS41211D-page 39
PIC12F683
4.2.5.6
GP5/T1CKI/OSC1/CLKIN
Figure 4-6 shows the diagram for this pin. The GP5 pin
is configurable to function as one of the following:
is configurable to function as one of the following:
• a general purpose I/O
• a Timer1 clock input
• a crystal/resonator connection
• a clock input
FIGURE 4-6:
BLOCK DIAGRAM OF GP5
TABLE 4-1:
SUMMARY OF REGISTERS ASSOCIATED WITH GPIO
I/O pin
V
DD
V
SS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
V
DD
D
EN
Q
D
EN
Q
Weak
Data
WR
WPU
RD
WPU
RD
GPIO
WR
GPIO
WR
TRISIO
RD
TRISIO
WR
IOC
RD
IOC
To Timer1 or CLKGEN
INTOSC
Mode
RD GPIO
INTOSC
Mode
GPPU
OSC2
(1)
Note
1: Timer1 LP oscillator enabled.
2: When using Timer1 with LP oscillator, the
Schmitt Trigger is bypassed.
TMR1LPEN
(1)
Interrupt-on-
change
Oscillator
Circuit
Bus
Q3
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
ANSEL
—
ADCS2
ADCS1
ADCS0
ANS3
ANS2
ANS1
ANS0
-000 1111
-000 1111
CCP1CON
—
—
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000
--00 0000
CMCON0
—
COUT
—
CINV
CIS
CM2
CM1
CM0
-0-0 0000
-0-0 0000
PCON
—
—
ULPWUE
SBOREN
—
—
POR
BOR
--01 --qq
--0u --uu
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 0000
0000 000x
IOC
—
—
IOC5
IOC4
IOC3
IOC2
IOC1
IOC0
--00 0000
--00 0000
OPTION_REG
GPPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
GPIO
—
—
GP5
GP4
GP3
GP2
GP1
GP0
--xx xxxx
--x0 x000
T1CON
T1GINV
TMR1GE
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
0000 0000
0000 0000
TRISIO
—
—
TRISIO5
TRISIO4
TRISIO3
TRISIO2
TRISIO1
TRISIO0
--11 1111
--11 1111
WPU
—
—
WPU5
WPU4
—
WPU2
WPU1
WPU0
--11 -111
--11 -111
Legend:
x
= unknown,
u
= unchanged, – = unimplemented locations read as ‘
0
’. Shaded cells are not used by GPIO.