Microchip Technology DM240015 Data Sheet
2012-2013 Microchip Technology Inc.
DS30009312B-page 275
PIC24FJ128GC010 FAMILY
19.3.1
CLEARING USB OTG INTERRUPTS
Unlike device level interrupts, the USB OTG interrupt
status flags are not freely writable in software. All USB
OTG flag bits are implemented as hardware set only
bits. Additionally, these bits can only be cleared in
software by writing a ‘1’ to their locations (i.e., perform-
ing a MOV type instruction). Writing a ‘0’ to a flag bit (i.e.,
a BCLR instruction) has no effect.
status flags are not freely writable in software. All USB
OTG flag bits are implemented as hardware set only
bits. Additionally, these bits can only be cleared in
software by writing a ‘1’ to their locations (i.e., perform-
ing a MOV type instruction). Writing a ‘0’ to a flag bit (i.e.,
a BCLR instruction) has no effect.
FIGURE 19-9:
EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS
19.4
Device Mode Operation
The following section describes how to perform a com-
mon Device mode task. In Device mode, USB transfers
are performed at the transfer level. The USB module
automatically performs the status phase of the transfer.
mon Device mode task. In Device mode, USB transfers
are performed at the transfer level. The USB module
automatically performs the status phase of the transfer.
19.4.1
ENABLING DEVICE MODE
1.
Reset the Ping-Pong Buffer Pointers by setting,
then clearing, the Ping-Pong Buffer Reset bit,
PPBRST (U1CON<1>).
then clearing, the Ping-Pong Buffer Reset bit,
PPBRST (U1CON<1>).
2.
Disable all interrupts (U1IE and U1EIE = 00h).
3.
Clear any existing interrupt flags by writing FFh
to U1IR and U1EIR.
to U1IR and U1EIR.
4.
Verify that V
BUS
is present (non-OTG devices
only).
5.
Enable the USB module by setting the USBEN
bit (U1CON<0>).
bit (U1CON<0>).
6.
Set the OTGEN bit (U1OTGCON<2>) to enable
OTG operation.
OTG operation.
7.
Enable the endpoint zero buffer to receive the
first setup packet by setting the EPRXEN and
EPHSHK bits for Endpoint 0 (U1EP0<3,0> = 1).
first setup packet by setting the EPRXEN and
EPHSHK bits for Endpoint 0 (U1EP0<3,0> = 1).
8.
Power up the USB module by setting the
USBPWR bit (U1PWRC<0>).
USBPWR bit (U1PWRC<0>).
9.
Enable the D+ pull-up resistor to signal an attach
by setting the DPPULUP bit (U1OTGCON<7>).
by setting the DPPULUP bit (U1OTGCON<7>).
Note:
Throughout this data sheet, a bit that can
only be cleared by writing a ‘1’ to its loca-
tion is referred to as “Write 1 to clear”. In
register descriptions, this function is
indicated by the descriptor, “K”.
only be cleared by writing a ‘1’ to its loca-
tion is referred to as “Write 1 to clear”. In
register descriptions, this function is
indicated by the descriptor, “K”.
USB Reset
SOF
RESET
SETUP
DATA
STATUS
SOF
SETUP Token
Data
ACK
OUT Token Empty Data
ACK
Start-of-Frame (SOF)
IN Token
Data
ACK
SOFIF
URSTIF
1 ms Frame
Differential Data
From Host From Host To Host
From Host
To Host
From Host
From Host From Host
To Host
Transaction
Control Transfer
(1)
Transaction
Complete
Note
1:
The control transfer shown here is only an example showing events that can occur for every transaction. Typical
control transfers will spread across multiple frames.
control transfers will spread across multiple frames.
Set TRNIF
Set TRNIF
Set TRNIF