Microchip Technology DM183021 Data Sheet
2010 Microchip Technology Inc.
DS39616D-page 243
PIC18F2331/2431/4331/4431
REGISTER 21-4:
ADCON3: A/D CONTROL REGISTER 3
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADRS1
ADRS0
—
SSRC4
(1)
SSRC3
(1)
SSRC2
(1)
SSRC1
(1)
SSRC0
(1)
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
ADRS<1:0>
: A/D Result Buffer Depth Interrupt Select Control for Continuous Loop Mode bits
The ADRS bits are ignored in Single-Shot mode.
00
00
= Interrupt is generated when each word is written to the buffer
01
= Interrupt is generated when the 2nd and 4th words are written to the buffer
10
= Interrupt is generated when the 4th word is written to the buffer
11
= Unimplemented
bit 5
Unimplemented:
Read as ‘0’
bit 4-0
SSRC<4:0>:
A/D Trigger Source Select bits
(1)
00000
= All triggers disabled
xxxx1
= External interrupt RC3/INT0 starts A/D sequence
xxx1x
= Timer5 starts A/D sequence
xx1xx
= Input Capture 1 (IC1) starts A/D sequence
x1xxx
= CCP2 compare match starts A/D sequence
1xxxx
= Power Control PWM module rising edge starts A/D sequence
Note 1:
The SSRC<4:0> bits can be set such that any of the triggers will start a conversion (e.g., SSRC<4:0> = 00101
will trigger the A/D conversion sequence when RC3/INT0 or Input Capture 1 event occurs).
will trigger the A/D conversion sequence when RC3/INT0 or Input Capture 1 event occurs).