Microchip Technology ARD00385 Data Sheet
2009-2011 Microchip Technology Inc.
DS39957D-page 123
PIC18F87K90 FAMILY
8.3
Reading the Data EEPROM Memory
To read a data memory location, the user must write the
address to the EEADRH:EEADR register pair, clear the
EEPGD control bit (EECON1<7>) and then set control
bit, RD (EECON1<0>). After one cycle, the data is
available in the EEDATA register; therefore, it can be
read after one NOP instruction. EEDATA will hold this
value until another read operation, or until it is written to
by the user (during a write operation). The basic
process is shown in
address to the EEADRH:EEADR register pair, clear the
EEPGD control bit (EECON1<7>) and then set control
bit, RD (EECON1<0>). After one cycle, the data is
available in the EEDATA register; therefore, it can be
read after one NOP instruction. EEDATA will hold this
value until another read operation, or until it is written to
by the user (during a write operation). The basic
process is shown in
8.4
Writing to the Data EEPROM
Memory
Memory
To write an EEPROM data location, the address must first
be written to the EEADRH:EEADR register pair and the
data written to the EEDATA register. The sequence in
be written to the EEADRH:EEADR register pair and the
data written to the EEDATA register. The sequence in
must be followed to initiate the write cycle.
The write will not begin if this sequence is not exactly
followed (write 0x55 to EECON2, write 0xAA to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code
followed (write 0x55 to EECON2, write 0xAA to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code
execution (i.e., runaway programs). The WREN bit
should be kept clear at all times, except when updating
the EEPROM. The WREN bit is not cleared by hardware.
After a write sequence has been initiated, EECON1,
EEADRH:EEADR and EEDATA cannot be modified.
The WR bit will be inhibited from being set unless the
WREN bit is set. The WREN bit must be set on a
previous instruction. Both WR and WREN cannot be
set with the same instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Interrupt Flag bit
(EEIF) is set. The user may either enable this interrupt,
or poll this bit. EEIF must be cleared by software.
should be kept clear at all times, except when updating
the EEPROM. The WREN bit is not cleared by hardware.
After a write sequence has been initiated, EECON1,
EEADRH:EEADR and EEDATA cannot be modified.
The WR bit will be inhibited from being set unless the
WREN bit is set. The WREN bit must be set on a
previous instruction. Both WR and WREN cannot be
set with the same instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Interrupt Flag bit
(EEIF) is set. The user may either enable this interrupt,
or poll this bit. EEIF must be cleared by software.
8.5
Write Verify
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
EXAMPLE 8-1:
DATA EEPROM READ
EXAMPLE 8-2:
DATA EEPROM WRITE
Note:
Self-write execution to Flash and
EEPROM memory cannot be done while
running in LP Oscillator mode (Low-Power
mode). Therefore, executing a self-write
will put the device into High-Power mode.
EEPROM memory cannot be done while
running in LP Oscillator mode (Low-Power
mode). Therefore, executing a self-write
will put the device into High-Power mode.
MOVLW
DATA_EE_ADDRH
;
MOVWF
EEADRH
; Upper bits of Data Memory Address to read
MOVLW
DATA_EE_ADDR
;
MOVWF
EEADR
; Lower bits of Data Memory Address to read
BCF
EECON1, EEPGD
; Point to DATA memory
BCF
EECON1, CFGS
; Access EEPROM
BSF
EECON1, RD
; EEPROM Read
NOP
MOVF
EEDATA, W
; W = EEDATA
MOVLW
DATA_EE_ADDRH
;
MOVWF
EEADRH
; Upper bits of Data Memory Address to write
MOVLW
DATA_EE_ADDR
;
MOVWF
EEADR
; Lower bits of Data Memory Address to write
MOVLW
DATA_EE_DATA
;
MOVWF
EEDATA
; Data Memory Value to write
BCF
EECON1, EEPGD
; Point to DATA memory
BCF
EECON1, CFGS
; Access EEPROM
BSF
EECON1, WREN
; Enable writes
BCF
INTCON, GIE
; Disable Interrupts
MOVLW
0x55
;
Required
MOVWF
EECON2
; Write 55h
Sequence
MOVLW
0xAA
;
MOVWF
EECON2
; Write 0AAh
BTFSC
EECON1, WR
; Wait for write to complete
GOTO
$-2
BSF
INTCON, GIE
; Enable Interrupts
; User code execution
BCF
EECON1, WREN
; Disable writes on write complete (EEIF set)