Microchip Technology MA300015 Data Sheet

© 2011 Microchip Technology Inc.

DS70150E-page 85

This section describes the output compare module and
associated operational modes. The features provided
by this module are useful in applications requiring
operational modes such as:

• Generation of Variable Width Output Pulses

• Power Factor Correction

 depicts a block diagram of the output

compare module.

The key operational features of the output compare
module include:

• Timer2 and Timer3 Selection mode

• Simple Output Compare Match mode

• Dual Output Compare Match mode

• Simple PWM mode

• Output Compare during Sleep and Idle modes

• Interrupt on Output Compare/PWM Event

These operating modes are determined by setting the
appropriate bits in the 16-bit OCxCON SFR (where
x = 1,2,3,...,N). The dsPIC30F6010A and
dsPIC30F6015 devices have eight compare channels.

OCxRS and OCxR in 

 represent the Dual

Compare registers. In the Dual Compare mode, the
OCxR register is used for the first compare and OCxRS
is used for the second compare. 

This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).

OCxR 

Comparator

 

    

Output

Logic

Q

S

R

OCM<2:0>

Output Enable

OCx

Set Flag bit

OCxIF

OCxRS 

Mode Select

3

Where ‘x’ is shown, reference is made to the registers associated with the respective output compare
channels 1 through N. 

OCFA        

 

    

OCTSEL

0

1

T2P2_MATCH

TMR2<15:0

TMR3<15:0>

T3P3_MATCH

From GP Timer Module

(for x = 1, 2, 3 or 4)

or OCFB

(for x = 5, 6, 7 or 8) 

0

1