Microchip Technology MA330031 Data Sheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 110
2011-2013 Microchip Technology Inc.
4.4.3
DATA MEMORY ARBITRATION AND
BUS MASTER PRIORITY
BUS MASTER PRIORITY
EDS accesses from bus masters in the system are
arbitrated.
The arbiter for data memory (including EDS) arbitrates
between the CPU, the DMA and the ICD module. In the
event of coincidental access to a bus by the bus
masters, the arbiter determines which bus master
access has the highest priority. The other bus masters
are suspended and processed after the access of the
bus by the bus master with the highest priority.
By default, the CPU is Bus Master 0 (M0) with the
highest priority and the ICD is Bus Master 4 (M4) with
the lowest priority. The remaining bus master (DMA
Controller) is allocated to M3 (M1 and M2 are reserved
and cannot be used). The user application may raise or
lower the priority of the DMA Controller to be above that
of the CPU by setting the appropriate bits in the EDS
Bus Master Priority Control (MSTRPR) register. All bus
masters with raised priorities will maintain the same
priority relationship relative to each other (i.e., M1
being highest and M3 being lowest, with M2 in
between). Also, all the bus masters with priorities below
arbitrated.
The arbiter for data memory (including EDS) arbitrates
between the CPU, the DMA and the ICD module. In the
event of coincidental access to a bus by the bus
masters, the arbiter determines which bus master
access has the highest priority. The other bus masters
are suspended and processed after the access of the
bus by the bus master with the highest priority.
By default, the CPU is Bus Master 0 (M0) with the
highest priority and the ICD is Bus Master 4 (M4) with
the lowest priority. The remaining bus master (DMA
Controller) is allocated to M3 (M1 and M2 are reserved
and cannot be used). The user application may raise or
lower the priority of the DMA Controller to be above that
of the CPU by setting the appropriate bits in the EDS
Bus Master Priority Control (MSTRPR) register. All bus
masters with raised priorities will maintain the same
priority relationship relative to each other (i.e., M1
being highest and M3 being lowest, with M2 in
between). Also, all the bus masters with priorities below
that of the CPU maintain the same priority relationship
relative to each other. The priority schemes for bus
masters with different MSTRPR values are tabulated in
relative to each other. The priority schemes for bus
masters with different MSTRPR values are tabulated in
This bus master priority control allows the user
application to manipulate the real-time response of the
system, either statically during initialization or
dynamically in response to real-time events.
application to manipulate the real-time response of the
system, either statically during initialization or
dynamically in response to real-time events.
TABLE 4-62:
DATA MEMORY BUS
ARBITER PRIORITY
ARBITER PRIORITY
FIGURE 4-18:
ARBITER ARCHITECTURE
Priority
MSTRPR<15:0> Bit Setting
0x0000
0x0020
M0 (highest)
CPU
DMA
M1
Reserved
CPU
M2
Reserved
Reserved
M3
DMA
Reserved
M4 (lowest)
ICD
ICD
Note 1:
All other values of MSTRPR<15:0> are
reserved.
reserved.
ICD
Reserved
Data Memory Arbiter
M0
M1
M2
M3
M4
MSTRPR<15:0>
DMA
CPU
SRAM