Microchip Technology MA330031 Data Sheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 140
2011-2013 Microchip Technology Inc.
In addition, DMA transfers can be triggered by timers
as well as external interrupts. Each DMA channel is
unidirectional. Two DMA channels must be allocated to
read and write to a peripheral. If more than one channel
receives a request to transfer data, a simple fixed
priority scheme based on channel number, dictates
which channel completes the transfer and which
channel, or channels, are left pending. Each DMA
channel moves a block of data, after which, it generates
an interrupt to the CPU to indicate that the block is
available for processing.
The DMA Controller provides these functional
capabilities:
• Four DMA channels
• Register Indirect with Post-Increment
as well as external interrupts. Each DMA channel is
unidirectional. Two DMA channels must be allocated to
read and write to a peripheral. If more than one channel
receives a request to transfer data, a simple fixed
priority scheme based on channel number, dictates
which channel completes the transfer and which
channel, or channels, are left pending. Each DMA
channel moves a block of data, after which, it generates
an interrupt to the CPU to indicate that the block is
available for processing.
The DMA Controller provides these functional
capabilities:
• Four DMA channels
• Register Indirect with Post-Increment
Addressing mode
• Register Indirect without Post-Increment
Addressing mode
• Peripheral Indirect Addressing mode (peripheral
generates destination address)
• CPU interrupt after half or full block
transfer complete
• Byte or word transfers
• Fixed priority channel arbitration
• Manual (software) or automatic (peripheral DMA
• Fixed priority channel arbitration
• Manual (software) or automatic (peripheral DMA
requests) transfer initiation
• One-Shot or Auto-Repeat Block Transfer modes
• Ping-Pong mode (automatic switch between two
• Ping-Pong mode (automatic switch between two
SRAM start addresses after each block transfer is
complete)
complete)
• DMA request for each channel can be selected
from any supported interrupt source
• Debug support features
The peripherals that can utilize DMA are listed in
The peripherals that can utilize DMA are listed in
.
TABLE 8-1:
DMA CHANNEL TO PERIPHERAL ASSOCIATIONS
Peripheral to DMA Association
DMAxREQ Register
IRQSEL<7:0> Bits
DMAxPAD Register
(Values to Read from
Peripheral)
DMAxPAD Register
(Values to Write to
Peripheral)
INT0 – External Interrupt 0
00000000
—
—
IC1 – Input Capture 1
00000001
0x0144 (IC1BUF)
—
IC2 – Input Capture 2
00000101
0x014C (IC2BUF)
—
IC3 – Input Capture 3
00100101
0x0154 (IC3BUF)
—
IC4 – Input Capture 4
00100110
0x015C (IC4BUF)
—
OC1 – Output Compare 1
00000010
—
0x0906 (OC1R)
0x0904 (OC1RS)
OC2 – Output Compare 2
00000110
—
0x0910 (OC2R)
0x090E (OC2RS)
OC3 – Output Compare 3
00011001
—
0x091A (OC3R)
0x0918 (OC3RS)
OC4 – Output Compare 4
00011010
—
0x0924 (OC4R)
0x0922 (OC4RS)
TMR2 – Timer2
00000111
—
—
TMR3 – Timer3
00001000
—
—
TMR4 – Timer4
00011011
—
—
TMR5 – Timer5
00011100
—
—
SPI1 Transfer Done
00001010
0x0248 (SPI1BUF)
0x0248 (SPI1BUF)
SPI2 Transfer Done
00100001
0x0268 (SPI2BUF)
0x0268 (SPI2BUF)
UART1RX – UART1 Receiver
00001011
0x0226 (U1RXREG)
—
UART1TX – UART1 Transmitter
00001100
—
0x0224 (U1TXREG)
UART2RX – UART2 Receiver
00011110
0x0236 (U2RXREG)
—
UART2TX – UART2 Transmitter
00011111
—
0x0234 (U2TXREG)
ECAN1 – RX Data Ready
00100010
0x0440 (C1RXD)
—
ECAN1 – TX Data Request
01000110
—
0x0442 (C1TXD)
ADC1 – ADC1 Convert Done
00001101
0x0300 (ADC1BUF0)
—