Microchip Technology AC244045 Data Sheet
© 2009 Microchip Technology Inc.
DS41341E-page 119
PIC16F72X/PIC16LF72X
TABLE 12-5:
WDT/TIMER1 GATE INTERACTION
12.6.3
TIMER1 GATE TOGGLE MODE
When Timer1 Gate Toggle mode is enabled, it is pos-
sible to measure the full-cycle length of a Timer1 gate
signal, as opposed to the duration of a single level
pulse.
sible to measure the full-cycle length of a Timer1 gate
signal, as opposed to the duration of a single level
pulse.
The Timer1 Gate source is routed through a flip-flop
that changes state on every incrementing edge of the
signal. See Figure 12-4 for timing details.
that changes state on every incrementing edge of the
signal. See Figure 12-4 for timing details.
Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
12.6.4
TIMER1 GATE SINGLE-PULSE
MODE
MODE
When Timer1 Gate Single-Pulse mode is enabled, it is
possible to capture a single pulse gate event. Timer1
Gate Single-Pulse mode is first enabled by setting the
T1GSPM bit in the T1GCON register. Next, the
T1GGO/DONE bit in the T1GCON register must be set.
The Timer1 will be fully enabled on the next
incrementing edge. On the next trailing edge of the
pulse, the T1GGO/DONE bit will automatically be
cleared. No other gate events will be allowed to
increment Timer1 until the T1GGO/DONE bit is once
again set in software.
possible to capture a single pulse gate event. Timer1
Gate Single-Pulse mode is first enabled by setting the
T1GSPM bit in the T1GCON register. Next, the
T1GGO/DONE bit in the T1GCON register must be set.
The Timer1 will be fully enabled on the next
incrementing edge. On the next trailing edge of the
pulse, the T1GGO/DONE bit will automatically be
cleared. No other gate events will be allowed to
increment Timer1 until the T1GGO/DONE bit is once
again set in software.
Clearing the T1GSPM bit of the T1GCON register will
also clear the T1GGO/DONE bit. See Figure 12-5 for
timing details.
also clear the T1GGO/DONE bit. See Figure 12-5 for
timing details.
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
together. This allows the cycle times on the Timer1
Gate source to be measured. See Figure 12-6 for
timing details.
simultaneously will permit both sections to work
together. This allows the cycle times on the Timer1
Gate source to be measured. See Figure 12-6 for
timing details.
12.6.5
TIMER1 GATE VALUE STATUS
When Timer1 Gate Value Status is utilized, it is possi-
ble to read the most current level of the gate control
value. The value is stored in the T1GVAL bit in the
T1GCON register. The T1GVAL bit is valid even when
the Timer1 Gate is not enabled (TMR1GE bit is
cleared).
ble to read the most current level of the gate control
value. The value is stored in the T1GVAL bit in the
T1GCON register. The T1GVAL bit is valid even when
the Timer1 Gate is not enabled (TMR1GE bit is
cleared).
12.6.6
TIMER1 GATE EVENT INTERRUPT
When Timer1 Gate Event Interrupt is enabled, it is pos-
sible to generate an interrupt upon the completion of a
gate event. When the falling edge of T1GVAL occurs,
the TMR1GIF flag bit in the PIR1 register will be set. If
the TMR1GIE bit in the PIE1 register is set, then an
interrupt will be recognized.
sible to generate an interrupt upon the completion of a
gate event. When the falling edge of T1GVAL occurs,
the TMR1GIF flag bit in the PIR1 register will be set. If
the TMR1GIE bit in the PIE1 register is set, then an
interrupt will be recognized.
The TMR1GIF flag bit operates even when the Timer1
Gate is not enabled (TMR1GE bit is cleared).
Gate is not enabled (TMR1GE bit is cleared).
WDTE
TMR1GE = 1
and
T1GSS = 11
WDT Oscillator
Enable
WDT Reset
Wake-up
WDT Available for
T1G Source
1
N
Y
Y
Y
N
1
Y
Y
Y
Y
Y
0
Y
Y
N
N
Y
0
N
N
N
N
N
Note:
Enabling Toggle mode at the same time as
changing the gate polarity may result in
indeterminate operation.
changing the gate polarity may result in
indeterminate operation.