Microchip Technology AC244045 Data Sheet

DS41341E-page 120

© 2009 Microchip Technology Inc.

The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit of the PIR1 register is
set. To enable the interrupt on rollover, you must set
these bits:

• TMR1ON bit of the T1CON register

• TMR1IE bit of the PIE1 register

• PEIE bit of the INTCON register

• GIE bit of the INTCON register

The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.

Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device:

• TMR1ON bit of the T1CON register must be set

• TMR1IE bit of the PIE1 register must be set

• PEIE bit of the INTCON register must be set

• T1SYNC bit of the T1CON register must be set

• TMR1CS bits of the T1CON register must be 

configured

• T1OSCEN bit of the T1CON register must be 

configured

• TMR1GIE bit of the T1GCON register must be 

configured

The device will wake-up on an overflow and execute
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine (0004h).

The CCP module uses the TMR1H:TMR1L register
pair as the time base when operating in Capture or
Compare mode.

In Capture mode, the value in the TMR1H:TMR1L
register pair is copied into the CCPR1H:CCPR1L
register pair on a configured event. 

In Compare mode, an event is triggered when the value
CCPR1H:CCPR1L register pair matches the value in
the TMR1H:TMR1L register pair. This event can be a
Special Event Trigger.

For more information, see Section 15.0
“Capture/Compare/PWM (CCP) Module”.

When the CCP is configured to trigger a special event,
the trigger will clear the TMR1H:TMR1L register pair.
This special event does not cause a Timer1 interrupt.
The CCP module may still be configured to generate a
CCP interrupt.

In this mode of operation, the CCPR1H:CCPR1L
register pair becomes the period register for Timer1.

Timer1 should be synchronized to the F

OSC

/4 to utilize

the Special Event Trigger. Asynchronous operation of
Timer1 can cause a Special Event Trigger to be
missed.

In the event that a write to TMR1H or TMR1L coincides
with a Special Event Trigger from the CCP, the write will
take precedence.

For more information, see Section 9.2.5 “Special
Event Trigger”.

The TMR1H:TMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.

T1CKI = 1

when TMR1
Enabled

T1CKI = 0

when TMR1
Enabled

Arrows indicate counter increments.

In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.