Microchip Technology AC244045 Data Sheet

© 2009 Microchip Technology Inc.

DS41341E-page 139

In Compare mode, the 16-bit CCPRx register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the CCPx module may:

• Toggle the CCPx output

• Set the CCPx output

• Clear the CCPx output

• Generate a Special Event Trigger

• Generate a Software Interrupt

The action on the pin is based on the value of the
CCPxM<3:0> control bits of the CCPxCON register.

All Compare modes can generate an interrupt.

15.2.1

CCPx PIN CONFIGURATION

The user must configure the CCPx pin as an output by
clearing the associated TRIS bit.

Either RC1 or RB3 can be selected as the CCP2 pin.
Refer to Section 6.1 “Alternate Pin Function” for
more information.

15.2.2

TIMER1 MODE SELECTION

In Compare mode, Timer1 must be running in either
Timer mode or Synchronized Counter mode. The
compare operation may not work in Asynchronous
Counter mode.

15.2.3

SOFTWARE INTERRUPT MODE 

When Software Interrupt mode is chosen
(CCPxM<3:0> = 1010), the CCPxIF bit in the PIRx
register is set and the CCPx module does not assert
control of the CCPx pin (refer to the CCPxCON
register).

15.2.4

SPECIAL EVENT TRIGGER

When Special Event Trigger mode is chosen
(CCPxM<3:0> = 1011), the CCPx module does the
following:

• Resets Timer1

• Starts an ADC conversion if ADC is enabled 

(CCP2 only)

The CCPx module does not assert control of the CCPx
pin in this mode (refer to the CCPxCON register).

The Special Event Trigger output of the CCP occurs
immediately upon a match between the TMR1H,
TMR1L register pair and the CCPRxH, CCPRxL
register pair. The TMR1H, TMR1L register pair is not
reset until the next rising edge of the Timer1 clock. This
allows the CCPRxH, CCPRxL register pair to
effectively provide a 16-bit programmable period
register for Timer1.

15.2.5

COMPARE DURING SLEEP

The Compare Mode is dependent upon the system
clock (F

OSC

) for proper operation. Since F

OSC

 is shut

down during Sleep mode, the Compare mode will not
function properly during Sleep.

Clearing the CCPxCON register will force
the CCPx compare output latch to the
default low level. This is not the PORT I/O
data latch.

CCPRxH CCPRxL

TMR1H

TMR1L

Comparator

Q

S

R

Output

Logic

Special Event Trigger

Set CCPxIF Interrupt Flag

(PIRx)

Match

TRIS

CCPxCON<3:0>

Mode Select

Output Enable

Special Event Trigger will:

•

Clear TMR1H and TMR1L registers.

•

NOT set interrupt flag bit TMR1IF of the PIR1 register.

•

Set the GO/DONE bit to start the ADC conversion 
(CCP2 only).

CCPx

4

Clocking Timer1 from the system clock
(F

OSC

) should not be used in Compare

mode. For the Compare operation of the
TMR1 register to the CCPRx register to
occur, Timer1 must be clocked from the
Instruction Clock (F

OSC

/4) or from an

external clock source.

Note 1: The Special Event Trigger from the CCP

module does not set interrupt flag bit
TMR1IF of the PIR1 register.

2: Removing the match condition by

changing the contents of the CCPRxH
and CCPRxL register pair, between the
clock edge that generates the Special
Event Trigger and the clock edge that
generates the Timer1 Reset, will preclude
the Reset from occurring.