Microchip Technology DM163025-1 Data Sheet
2012 Microchip Technology Inc.
DS30684A-page 277
PIC18(L)F2X/45K50
FIGURE 17-5:
ASYNCHRONOUS RECEPTION
Start
bit
bit 7/8
bit 1
bit 0
bit 7/8
bit 0
Stop
bit
Start
bit
Start
bit
bit 7/8 Stop
bit
RX/DT pin
Reg
Rcv Buffer Reg
Rcv Shift
Read Rcv
Buffer Reg
RCREGx
RCIF
(Interrupt Flag)
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREGx
Word 2
RCREGx
Stop
bit
Note:
This timing diagram shows three words appearing on the RX/DT input. The RCREGx (receive buffer) is read after the third
word, causing the OERR (overrun) bit to be set.
word, causing the OERR (overrun) bit to be set.
RCIDL
TABLE 17-2:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on page
BAUDCON1
ABDOVF
RCIDL
RXDTP
TXCKP
BRG16
—
WUE
ABDEN
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
IOCIE
TMR0IF
INT0IF
IOCIF
IPR1
ACTIP
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
PIE1
ACTIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
PIR1
ACTIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
PMD0
—
UARTMD
USBMD
ACTMD
—
TMR3MD
TMR2MD
TMR1MD
RCREG1
EUSART Receive Register
—
RCSTA1
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
SPBRG1
EUSART Baud Rate Generator, Low Byte
—
SPBRGH1
EUSART Baud Rate Generator, High Byte
—
TRISC
TRISC7
TRISC6
—
—
—
TRISC2
TRISC1
TRISC0
TXSTA1
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
Legend:
— = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous reception.