Microchip Technology DM163025-1 Data Sheet
2012 Microchip Technology Inc.
DS30684A-page 279
PIC18(L)F2X/45K50
17.3
Register Definitions: EUSART Control
REGISTER 17-1:
TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-1
R/W-0
CSRC
TX9
TXEN
(1)
SYNC
SENDB
BRGH
TRMT
TX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
CSRC:
Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1
Don’t care
Synchronous mode:
1
= Master mode (clock generated internally from BRG)
0
= Slave mode (clock from external source)
bit 6
TX9:
9-bit Transmit Enable bit
1
= Selects 9-bit transmission
0
= Selects 8-bit transmission
bit 5
TXEN:
Transmit Enable bit
(1)
1
= Transmit enabled
0
= Transmit disabled
bit 4
SYNC:
EUSART Mode Select bit
1
= Synchronous mode
0
= Asynchronous mode
bit 3
SENDB:
Send Break Character bit
Asynchronous mode:
1
1
= Send Sync Break on next transmission (cleared by hardware upon completion)
0
= Sync Break transmission completed
Synchronous mode:
Don’t care
Don’t care
bit 2
BRGH:
High Baud Rate Select bit
Asynchronous mode:
1
1
= High speed
0
= Low speed
Synchronous mode:
Unused in this mode
Unused in this mode
bit 1
TRMT:
Transmit Shift Register Status bit
1
= TSR empty
0
= TSR full
bit 0
TX9D:
Ninth bit of Transmit Data
Can be address/data bit or a parity bit.
Note
1:
SREN/CREN overrides TXEN in Sync mode.