Microchip Technology MA330024 Data Sheet
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS70000591F-page 122
2009-2014 Microchip Technology Inc.
6.9
Using the RCON Status Bits
The user application can read the Reset Control
(RCON) register after any device Reset to determine
the cause of the Reset.
(RCON) register after any device Reset to determine
the cause of the Reset.
provides a summary of the Reset flag bit
operation.
TABLE 6-3:
RESET FLAG BIT OPERATION
Note:
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
Flag Bit
Set by:
Cleared by:
TRAPR (RCON<15>)
Trap Conflict Event
POR, BOR
IOPWR (RCON<14>)
Illegal Opcode or Uninitialized W register
Access or Security Reset
Access or Security Reset
POR, BOR
EXTR (RCON<7>)
MCLR Reset
POR
SWR (RCON<6>)
RESET
Instruction
POR, BOR
WDTO (RCON<4>)
WDT Time-out
PWRSAV
Instruction, CLRWDT Instruction,
POR, BOR
SLEEP (RCON<3>)
PWRSAV #SLEEP
Instruction
POR, BOR
IDLE (RCON<2>)
PWRSAV #IDLE
Instruction
POR, BOR
BOR (RCON<1>)
POR, BOR
—
POR (RCON<0>)
POR
—
Note:
All Reset flag bits can be set or cleared by user software.