Microchip Technology MA330024 Data Sheet

 2009-2014 Microchip Technology Inc.

DS70000591F-page 127

The dsPIC33FJ32GS406/606/608/610 and
dsPIC33FJ64GS406/606/608/610 devices implement
44 registers for the interrupt controller: 

• INTCON1 
• INTCON2 
• IFSx
• IECx
• IPCx 
• INTTREG

7.3.1

INTCON1 AND INTCON2

Global interrupt control functions are controlled from
INTCON1 and INTCON2. INTCON1 contains the
Interrupt Nesting Disable (NSTDIS) bit as well as the
control and status flags for the processor trap sources.
The INTCON2 register controls the external interrupt
request signal behavior and the use of the Alternate
Interrupt Vector Table.

7.3.2

IFSx

The IFSx registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or external signal and
is cleared via software.

7.3.3

IECx

The IECx registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.

7.3.4

IPCx

The IPCx registers are used to set the Interrupt Priority
Level for each source of interrupt. Each user interrupt
source can be assigned to one of eight priority levels. 

7.3.5

INTTREG

The INTTREG register contains the associated
interrupt vector number and the new CPU Interrupt
Priority Level, which are latched into the Vector Num-
ber (VECNUM<6:0>) and Interrupt Level (ILR<3:0>) bit
fields in the INTTREG register. The new Interrupt
Priority Level is the priority of the pending interrupt. 

The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence that they are
listed in 

. For example, the INT0 (External

Interrupt 0) is shown as having vector number 8 and a
natural order priority of 0. Thus, the INT0IF bit is found
in IFS0<0>, the INT0IE bit is found in IEC0<0> and the
INT0IP bits are found in the first position of IPC0
(IPC0<2:0>). 

7.3.6

STATUS/CONTROL REGISTERS

Although they are not specifically part of the interrupt
control hardware, two of the CPU Control registers
contain bits that control interrupt functionality.

• The CPU STATUS Register, SR, contains the

IPL<2:0> bits (SR<7:5>). These bits indicate the
current CPU Interrupt Priority Level. The user can
change the current CPU Priority Level by writing
to the IPLx bits. 

• The CORCON register contains the IPL3 bit,

which together with IPL<2:0>, indicates the
current CPU Priority Level. IPL3 is a read-only bit
so that trap events cannot be masked by the user
software.

All Interrupt registers are described in 

through 

 in the following pages.